Composite oxide semiconductor and method for manufacturing the same

ABSTRACT

The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. A semiconductor layer of a transistor is formed using a composite oxide semiconductor in which a first region and a second region are mixed. The first region includes a plurality of first clusters containing one or more of indium, zinc, and oxygen as a main component. The second region includes a plurality of second clusters containing one or more of indium, an element M (M represents Al, Ga, Y, or Sn), zinc, and oxygen. The first region includes a portion in which the plurality of first clusters are connected to each other. The second region includes a portion in which the plurality of second clusters are connected to each other.

BACKGROUND OF THE INVENTION 1. Field of the Invention

One embodiment of the present invention relates to a semiconductordevice including an oxide semiconductor film and a display deviceincluding the semiconductor device.

Note that one embodiment of the present invention is not limited to theabove technical field. The technical field of one embodiment of theinvention disclosed in this specification and the like relates to asemiconductor device, a display device, a light-emitting device, a powerstorage device, a memory device, a driving method thereof, or amanufacturing method thereof.

In this specification and the like, a semiconductor device generallymeans a device that can function by utilizing semiconductorcharacteristics. A semiconductor element such as a transistor, asemiconductor circuit, an arithmetic device, and a memory device areeach one embodiment of a semiconductor device. An imaging device, adisplay device, a liquid crystal display device, a light-emittingdevice, an electro-optical device, a power generation device (includinga thin film solar cell, an organic thin film solar cell, and the like),and an electronic device may each include a semiconductor device.

2. Description of the Related Art

Attention has been focused on a technique for forming a transistor usinga semiconductor thin film formed over a substrate having an insulatingsurface (also referred to as a field-effect transistor (FET) or a thinfilm transistor (TFT)). Such transistors are used in a wide range ofelectronic devices such as an integrated circuit (IC) and an imagedisplay device (display device). A semiconductor material typified bysilicon is widely known as a material for a semiconductor thin film thatcan be used for a transistor. As another material, an oxidesemiconductor has been attracting attention.

In addition, a semiconductor device achieving high field-effect mobility(simply referred to as mobility or μ_(FE) in some cases) with such astructure that a plurality of oxide semiconductor layers are stacked,the oxide semiconductor layer serving as a channel in the plurality ofoxide semiconductor layers contains indium and gallium, and theproportion of indium is higher than the proportion of gallium (seePatent Document 1).

REFERENCE Patent Document

-   [Patent Document 1] Japanese Published Patent Application No.    2014-007399

SUMMARY OF THE INVENTION

The field-effect mobility of a transistor that uses an oxidesemiconductor film as a channel region is preferably as high aspossible. However, when the field-effect mobility is increased, thetransistor has a problem with its characteristics, that is, thetransistor tends to be normally on. Note that “normally on” means astate where a channel exists without application of a voltage to a gateelectrode and current flows through the transistor.

Furthermore, in a transistor that uses an oxide semiconductor film in achannel region, oxygen vacancies which are formed in the oxidesemiconductor film adversely affect the transistor characteristics. Forexample, oxygen vacancies formed in the oxide semiconductor film arebonded with hydrogen to serve as carrier supply sources. The carriersupply sources generated in the oxide semiconductor film cause a changein the electrical characteristics, typically, shift in the thresholdvoltage, of the transistor including the oxide semiconductor film.

When the amount of oxygen vacancies in the oxide semiconductor film istoo large, for example, the threshold voltage of the transistor isshifted in the negative direction, and the transistor has normally-oncharacteristics. Thus, especially in the channel region of the oxidesemiconductor film, the amount of oxygen vacancies is preferably smallor the amount with which the normally-on characteristics are notexhibited.

In view of the foregoing problems, an object of one embodiment of thepresent invention is to improve field-effect mobility and reliability ofa transistor including an oxide semiconductor film. Another object ofone embodiment of the present invention is to prevent a change inelectrical characteristics of a transistor including an oxidesemiconductor film and to improve the reliability of the transistor.Another object of one embodiment of the present invention is to providea semiconductor device with reduced power consumption. Another object ofone embodiment of the present invention is to provide a novelsemiconductor device. Another object of one embodiment of the presentinvention is to provide a novel display device.

Note that the description of the above objects does not disturb theexistence of other objects. In one embodiment of the present invention,there is no need to achieve all of these objects. Objects other than theabove objects will be apparent from and can be derived from thedescription of the specification and the like.

One embodiment of the present invention is a composite oxidesemiconductor in which a first region and a second region are mixed. Thefirst region includes a plurality of first clusters containing one ormore of indium (In), zinc (Zn), and oxygen (O) as a main component. Thesecond region includes a plurality of second clusters containing one ormore of indium, an element M (M represents Al, Ga, Y, or Sn), zinc, andoxygen as a main component. The first region includes a portion in whichthe plurality of first clusters are connected to each other, and thesecond region includes a portion in which the plurality of secondclusters are connected to each other.

In the above embodiment, the first region preferably exists beingsurrounded by the second region.

In the above embodiments, the first clusters preferably have higherconductivity than the second clusters, and the second clusterspreferably have a higher semiconductor property than the first clusters.

Furthermore, the composite oxide semiconductor preferably includes aportion in which each of the first clusters has a size of greater thanor equal to 0.5 nm and less than or equal to 1.5 nm.

In the above embodiments, it is preferable that an atomic ratio of In toan element M and Zn be In:M:Zn=4:2:3 or in a neighborhood thereof, andthe proportion of the element M be higher than or equal to 1.5 and lowerthan or equal to 2.5 and the proportion of Zn be higher than or equal to2 and lower than or equal to 4 when the proportion of In is 4.

Alternatively, in the above embodiments, it is preferable that an atomicratio of In to an element M and Zn be In:M:Zn=5:1:6 or in a neighborhoodthereof, and the proportion of the element M be higher than or equal to0.5 and lower than or equal to 1.5 and the proportion of Zn be higherthan or equal to 5 and lower than or equal to 7 when the proportion ofIn is 5.

One embodiment of the present invention is a semiconductor deviceincluding a semiconductor layer, a gate, and a gate insulating layer.The semiconductor layer includes the composite oxide semiconductordescribed in any of the above embodiments. At this time, it ispreferable that a maximum value of field-effect mobility be greater thanor equal to 100 cm²/Vs and less than or equal to 200 cm²/Vs in a rangein which a gate voltage is higher than 0 V and lower than or equal to 10V and a drain voltage is higher than 0 V and lower than or equal to 20V.

Another embodiment of the present invention is a method formanufacturing a composite oxide semiconductor, which includes a firststep of placing a substrate in a deposition chamber; a second step ofintroducing one or both of an argon gas and an oxygen gas into thedeposition chamber; a third step of applying voltage to a targetcontaining indium, an element M (M represents Al, Ga, Y, or Sn), zinc,and oxygen; and a fourth step of depositing the composite oxidesemiconductor from the target onto the substrate. The fourth stepincludes a first step in which the element M and the zinc arepreferentially sputtered from the target; and a second step in which theindium has a cluster-like shape and then the indium with thecluster-like shape is sputtered from the target.

Another embodiment of the present invention is a method formanufacturing a composite oxide semiconductor, which includes a firststep of placing a substrate in a deposition chamber; a second step ofintroducing, into the deposition chamber, a deposition gas containing anargon gas and not containing an oxygen gas; a third step of applyingvoltage to a target containing indium, an element M (M represents Al,Ga, Y, or Sn), zinc, and oxygen; and a fourth step of depositing thecomposite oxide semiconductor from the target onto the substrate. Thefourth step includes a first step in which the element M and the zincare preferentially sputtered from the target; and a second step in whichthe indium has a cluster-like shape and then the indium with thecluster-like shape is sputtered from the target.

In the above manufacturing methods, it is preferable that the substratenot be heated intentionally.

Another embodiment of the present invention is a display device whichincludes the semiconductor device of any one of the above-describedembodiments, and a display element. Another embodiment of the presentinvention is a display module which includes the display device and atouch sensor. Another embodiment of the present invention is anelectronic device which includes the semiconductor device of any one ofthe above-described embodiments, the above-described display device, orthe above-described display module; and an operation key or a battery.

One embodiment of the present invention can improve field-effectmobility and reliability of a transistor including an oxidesemiconductor film. One embodiment of the present invention can preventa change in electrical characteristics of a transistor including anoxide semiconductor film and improve the reliability of the transistor.One embodiment of the present invention can provide a semiconductordevice with reduced power consumption. One embodiment of the presentinvention can provide a novel semiconductor device. One embodiment ofthe present invention can provide a novel display device.

Note that the description of these effects does not preclude theexistence of other effects. One embodiment of the present invention doesnot necessarily have all the effects listed above. Other effects can bederived from the description of the specification, the drawings, theclaims, and the like.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are a schematic top view and a schematic cross-sectionalview illustrating a composite oxide semiconductor.

FIG. 2 illustrates atomic ratios of an oxide semiconductor.

FIGS. 3A and 3B are a schematic top view and a schematic cross-sectionalview illustrating a composite oxide semiconductor.

FIGS. 4A and 4B are a schematic top view and a schematic cross-sectionalview illustrating a composite oxide semiconductor.

FIGS. 5A and 5B are a schematic top view and a schematic cross-sectionalview illustrating a composite oxide semiconductor.

FIGS. 6A and 6B are a schematic top view and a schematic cross-sectionalview illustrating a composite oxide semiconductor.

FIGS. 7A and 7B illustrate a sputtering apparatus.

FIG. 8 is a process flow chart illustrating a method for manufacturing acomposite oxide semiconductor.

FIGS. 9A to 9C illustrate a cross section of the vicinity of a target.

FIG. 10 illustrates an analysis method.

FIG. 11 shows SEM observation and EDX mapping images.

FIG. 12 shows SEM observation and EDX mapping images.

FIGS. 13A and 13B show compositions of a sample.

FIG. 14 shows compositions of a sample.

FIG. 15 shows SEM observation and EDX mapping images.

FIG. 16 shows SEM observation and EDX mapping images.

FIG. 17 shows SEM observation and EDX mapping images.

FIG. 18 shows SEM observation and EDX mapping images.

FIG. 19 shows SEM observation and EDX mapping images.

FIG. 20 shows SEM observation and EDX mapping images.

FIGS. 21A to 21C are a top view and cross-sectional views illustrating asemiconductor device.

FIG. 22 is a cross-sectional view illustrating a semiconductor device.

FIGS. 23A and 23B are cross-sectional views illustrating a semiconductordevice.

FIGS. 24A and 24B are cross-sectional views illustrating a semiconductordevice.

FIGS. 25A and 25B are cross-sectional views illustrating a semiconductordevice.

FIGS. 26A and 26B are cross-sectional views illustrating a semiconductordevice.

FIGS. 27A and 27B are cross-sectional views illustrating a semiconductordevice.

FIGS. 28A and 28B are cross-sectional views illustrating a semiconductordevice.

FIGS. 29A and 29B are cross-sectional views illustrating a semiconductordevice.

FIGS. 30A and 30B are cross-sectional views illustrating a semiconductordevice.

FIGS. 31A to 31C each illustrate a band structure.

FIGS. 32A to 32C are a top view and cross-sectional views illustrating asemiconductor device.

FIGS. 33A to 33C are a top view and cross-sectional views illustrating asemiconductor device.

FIGS. 34A to 34C are a top view and cross-sectional views illustrating asemiconductor device.

FIGS. 35A to 35C are a top view and cross-sectional views illustrating asemiconductor device.

FIGS. 36A and 36B are cross-sectional views illustrating a semiconductordevice.

FIGS. 37A and 37B are cross-sectional views illustrating a semiconductordevice.

FIGS. 38A to 38C are a top view and cross-sectional views illustrating asemiconductor device.

FIG. 39 is a top view illustrating one mode of a display device.

FIG. 40 is a cross-sectional view illustrating one mode of a displaydevice.

FIG. 41 is a cross-sectional view illustrating one mode of a displaydevice.

FIG. 42 is a cross-sectional view illustrating one mode of a displaydevice.

FIG. 43 is a cross-sectional view illustrating one mode of a displaydevice.

FIG. 44 is a cross-sectional view illustrating one mode of a displaydevice.

FIGS. 45A to 45D are cross-sectional views illustrating a method forforming an EL layer.

FIG. 46 is a conceptual diagram illustrating a droplet dischargeapparatus.

FIGS. 47A to 47C are a block diagram and circuit diagrams illustrating adisplay device.

FIG. 48 illustrates a display module.

FIGS. 49A to 49E illustrate electronic devices.

FIGS. 50A to 50G illustrate electronic devices.

FIGS. 51A and 51B are perspective views illustrating a display device.

FIGS. 52A to 52E are a HAADF-STEM image and EDX mapping images of aplane.

FIGS. 53A to 53E are a HAADF-STEM image and EDX mapping images of across section.

FIG. 54 shows XRD analysis results.

FIG. 55 shows I_(d)-V_(g) characteristics of a transistor.

FIG. 56 shows I_(d)-V_(g) characteristics of a transistor.

FIG. 57 is a cross-sectional STEM image of a transistor.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiments will be described with reference to drawings.However, the embodiments can be implemented in many different modes, andit will be readily appreciated by those skilled in the art that modesand details thereof can be changed in various ways without departingfrom the spirit and scope of the present invention. Thus, the presentinvention should not be interpreted as being limited to the followingdescription of the embodiments.

In the drawings, the size, the layer thickness, or the region isexaggerated for clarity in some cases. Therefore, embodiments of thepresent invention are not limited to such a scale. Note that thedrawings are schematic views showing ideal examples, and embodiments ofthe present invention are not limited to shapes or values shown in thedrawings.

Note that in this specification, ordinal numbers such as “first”,“second”, and “third” are used in order to avoid confusion amongcomponents, and the terms do not limit the components numerically.

Note that in this specification, terms for describing arrangement, suchas “over”, “above”, “under”, and “below”, are used for convenience indescribing a positional relation between components with reference todrawings. Further, the positional relation between components is changedas appropriate in accordance with a direction in which the componentsare described. Thus, the positional relation is not limited to thatdescribed with a term used in this specification and can be explainedwith another term as appropriate depending on the situation.

In this specification and the like, a transistor is an element having atleast three terminals of a gate, a drain, and a source. In addition, thetransistor has a channel region between a drain (a drain terminal, adrain region, or a drain electrode) and a source (a source terminal, asource region, or a source electrode), and current can flow between thesource and the drain through the channel region. Note that in thisspecification and the like, a channel region refers to a region throughwhich current mainly flows.

Further, functions of a source and a drain might be switched whentransistors having different polarities are employed or a direction ofcurrent flow is changed in circuit operation, for example. Therefore,the terms “source” and “drain” can be switched in this specification andthe like.

Note that in this specification and the like, the expression“electrically connected” includes the case where components areconnected through an “object having any electric function”. There is noparticular limitation on an “object having any electric function” aslong as electric signals can be transmitted and received betweencomponents that are connected through the object. Examples of an “objecthaving any electric function” include a switching element such as atransistor, a resistor, an inductor, a capacitor, and elements with avariety of functions as well as an electrode and a wiring.

In this specification and the like, the term “parallel” means that theangle formed between two straight lines is greater than or equal to −10°and less than or equal to 10°, and accordingly also covers the casewhere the angle is greater than or equal to −5° and less than or equalto 5°. The term “perpendicular” means that the angle formed between twostraight lines is greater than or equal to 80° and less than or equal to100°, and accordingly also covers the case where the angle is greaterthan or equal to 85° and less than or equal to 95°.

In this specification and the like, the terms “film” and “layer” can beinterchanged with each other. For example, the term “conductive layer”can be changed into the term “conductive film” in some cases. Also, theterm “insulating film” can be changed into the term “insulating layer”in some cases.

Unless otherwise specified, the off-state current in this specificationand the like refers to a drain current of a transistor in an off state(also referred to as non-conduction state and cutoff state). Unlessotherwise specified, the off state of an n-channel transistor means thata voltage (V_(gs)) between its gate and source is lower than thethreshold voltage (V_(th)), and the off state of a p-channel transistormeans that the gate-source voltage V_(gs) is higher than the thresholdvoltage V_(th). For example, the off-state current of an n-channeltransistor sometimes refers to a drain current that flows when thegate-source voltage V_(gs) is lower than the threshold voltage V_(th).

The off-state current of a transistor depends on V_(gs) in some cases.Thus, “the off-state current of a transistor is lower than or equal toI” may mean “there is V_(gs) with which the off-state current of thetransistor becomes lower than or equal to I”. Furthermore, “theoff-state current of a transistor” means “the off-state current in anoff state at predetermined V_(gs)”, “the off-state current in an offstate at V_(gs) in a predetermined range”, “the off-state current in anoff state at V_(gs) with which sufficiently reduced off-state current isobtained”, or the like.

As an example, the assumption is made of an n-channel transistor wherethe threshold voltage V_(th) is 0.5 V and the drain current is 1×10⁻⁹ Aat V_(gs) of 0.5 V, 1×10⁻¹³ A at V_(gs) of 0.1 V, 1×10⁻¹⁹ A at V_(gs) of−0.5 V, and 1×10⁻²² A at V_(gs) of −0.8 V. The drain current of thetransistor is 1×10⁻¹⁹ A or lower at V_(gs) of −0.5 V or at V_(gs) in therange of −0.8 V to −0.5 V; therefore, it can be said that the off-statecurrent of the transistor is 1×10⁻¹⁹ A or lower. Since there is V_(gs)at which the drain current of the transistor is 1×10⁻²² A or lower, itmay be said that the off-state current of the transistor is 1×10⁻²² A orlower.

In this specification and the like, the off-state current of atransistor with a channel width W is sometimes represented by a currentvalue in relation to the channel width W or by a current value per givenchannel width (e.g., 1 μm). In the latter case, the off-state currentmay be expressed in the unit with the dimension of current per length(e.g., A/μm).

The off-state current of a transistor depends on temperature in somecases. Unless otherwise specified, the off-state current in thisspecification may be an off-state current at room temperature, 60° C.,85° C., 95° C., or 125° C. Alternatively, the off-state current may bean off-state current at a temperature at which the required reliabilityof a semiconductor device or the like including the transistor isensured or a temperature at which the semiconductor device or the likeincluding the transistor is used (e.g., temperature in the range of 5°C. to 35° C.). The description “an off-state current of a transistor islower than or equal to I” may refer to a situation where there is V_(gs)at which the off-state current of a transistor is lower than or equal toI at room temperature, 60° C., 85° C., 95° C., 125° C., a temperature atwhich the required reliability of a semiconductor device or the likeincluding the transistor is ensured, or a temperature at which thesemiconductor device or the like including the transistor is used (e.g.,temperature in the range of 5° C. to 35° C.).

The off-state current of a transistor depends on voltage V_(ds) betweenits drain and source in some cases. Unless otherwise specified, theoff-state current in this specification may be an off-state current atV_(ds) of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12V, 16 V, or 20 V. Alternatively, the off-state current may be anoff-state current at V_(ds) at which the required reliability of asemiconductor device or the like including the transistor is ensured orV_(ds) at which the semiconductor device or the like including thetransistor is used. The description “an off-state current of atransistor is lower than or equal to I” may refer to a situation wherethere is V_(gs) at which the off-state current of a transistor is lowerthan or equal to I at V_(ds) of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V,3 V, 3.3 V, 10 V, 12 V, 16 V, or 20 V, V_(ds) at which the requiredreliability of a semiconductor device or the like including thetransistor is ensured, or V_(ds) at which the semiconductor device orthe like including the transistor is used.

In the above description of off-state current, a drain may be replacedwith a source. That is, the off-state current sometimes refers tocurrent that flows through a source of a transistor in an off state.

In this specification and the like, the term “leakage current” sometimesexpresses the same meaning as off-state current. In this specificationand the like, the off-state current sometimes refers to current thatflows between a source and a drain when a transistor is off, forexample.

In this specification and the like, the threshold voltage of atransistor refers to a gate voltage (V_(g)) at which a channel is formedin the transistor. Specifically, in a graph where the horizontal axisrepresents the gate voltage (V_(g)) and the vertical axis represents thesquare root of drain current (I_(d)), the threshold voltage of atransistor may refer to a gate voltage (V_(g)) at the intersection ofthe square root of drain current (I_(d)) of 0 (I_(d)=0 A) and anextrapolated straight line that is tangent with the highest inclinationto a plotted curve (V_(g)-√I_(d) characteristics). Alternatively, thethreshold voltage of a transistor may refer to a gate voltage (V_(g)) atwhich the value of I_(d) [A]×L [μm]/W [μm] is 1×10⁻⁹ [A] where L ischannel length and W is channel width.

In this specification and the like, a “semiconductor” can havecharacteristics of an “insulator” when the conductivity is sufficientlylow, for example. Further, a “semiconductor” and an “insulator” cannotbe strictly distinguished from each other in some cases because a borderbetween the “semiconductor” and the “insulator” is not clear.Accordingly, a “semiconductor” in this specification and the like can becalled an “insulator” in some cases. Similarly, an “insulator” in thisspecification and the like can be called a “semiconductor” in somecases. An “insulator” in this specification and the like can be called a“semi-insulator” in some cases.

In this specification and the like, a “semiconductor” can havecharacteristics of a “conductor” when the conductivity is sufficientlyhigh, for example. Further, a “semiconductor” and a “conductor” cannotbe strictly distinguished from each other in some cases because a borderbetween the “semiconductor” and the “conductor” is not clear.Accordingly, a “semiconductor” in this specification and the like can becalled a “conductor” in some cases. Similarly, a “conductor” in thisspecification and the like can be called a “semiconductor” in somecases.

In this specification and the like, an impurity in a semiconductorrefers to an element that is not a main component of the semiconductor.For example, an element with a concentration of lower than 0.1 atomic %is an impurity. If a semiconductor contains an impurity, the density ofstates (DOS) may be formed therein, the carrier mobility may bedecreased, or the crystallinity may be decreased, for example. In thecase where the semiconductor includes an oxide semiconductor, examplesof the impurity which changes the characteristics of the semiconductorinclude Group 1 elements, Group 2 elements, Group 14 elements, Group 15elements, and transition metals other than the main components; specificexamples include hydrogen (also included in water), lithium, sodium,silicon, boron, phosphorus, carbon, and nitrogen. When the semiconductoris an oxide semiconductor, oxygen vacancies may be formed by entry ofimpurities such as hydrogen, for example. Furthermore, in the case wherethe semiconductor includes silicon, examples of the impurity whichchanges the characteristics of the semiconductor include oxygen, Group 1elements except hydrogen, Group 2 elements, Group 13 elements, and Group15 elements.

Embodiment 1

In this embodiment, an oxide semiconductor film that includes acomposite oxide semiconductor of one embodiment of the present inventionand a semiconductor device that includes this oxide semiconductor filmare described.

<1-1. Oxide Semiconductor Film>

Indium is preferably contained in an oxide semiconductor film. Inparticular, indium and zinc are preferably contained. In addition,aluminum, gallium, yttrium, tin, or the like is preferably contained.Furthermore, one or more elements selected from boron, silicon,titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum,cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the likemay be contained.

Here, the case where an oxide semiconductor film contains indium, anelement M, and zinc is considered. The element M is aluminum, gallium,yttrium, tin, or the like. Other elements that can be used as theelement M include boron, silicon, titanium, iron, nickel, germanium,zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum,tungsten, and magnesium. Note that two or more of the above elements canbe used in combination as the element M. The terms of the atomic ratioof indium, the element M, and zinc contained in the oxide semiconductorfilm are denoted by [In], [M], and [Zn], respectively.

<1-2. Structure of Oxide Semiconductor Film>

FIGS. 1A and 1B are schematic views of an oxide semiconductor film thatincludes a composite oxide semiconductor of one embodiment of thepresent invention.

FIG. 1A is a schematic view of a top surface of an oxide semiconductorfilm (a-b plane direction), and FIG. 1B is a schematic view of a crosssection of the oxide semiconductor film (c-axis direction) formed over asubstrate Sub.

FIGS. 1A and 1B illustrate an example in which the oxide semiconductorfilm is formed over the substrate; however, one embodiment of thepresent invention is not limited to this example and an insulating filmsuch as a base film or an interlayer film or another semiconductor filmsuch as an oxide semiconductor film may be formed between the substrateand the oxide semiconductor film.

The oxide semiconductor film of one embodiment of the present inventionis a composite oxide semiconductor having a structure in which Region A1and Region B1 are mixed as shown in FIGS. 1A and 1B. Therefore, in thefollowing description, the oxide semiconductor film is referred to as acomposite oxide semiconductor in some cases.

Region A1 shown in FIGS. 1A and 1B is high in In with[In]:[M]:[Zn]=x:y:z (x>0, y≥0, z≥0). In contrast, Region B1 is low in Inwith [In]:[M]:[Zn]=a:b:c (a>0, b>0, c>0).

Note that in this specification, when the atomic ratio of In to theelement M in Region A1 is greater than the atomic ratio of In to theelement M in Region B1, Region A1 has higher In concentration thanRegion B1. Therefore, in this specification, Region A1 is also referredto as an In-rich region, and Region B1 is also referred to as an In-poorregion.

For example, the In concentration in Region A1 is 1.1 or more times,preferably 2 to 10 times that in Region B1. Region A1 is an oxidecontaining at least In and does not necessarily contain the element Mand Zn.

The atomic ratio of elements included in the composite oxidesemiconductor of one embodiment of the present invention will bedescribed here.

A phase diagram in FIG. 2 can be used to show the atomic ratio ofelements in the case where Region A1 in the composite oxidesemiconductor contains In, the element M, and Zn. The atomic ratio of Into the element M and Zn is denoted by x:y:z. This atomic ratio can beshown as coordinates (x:y:z) in FIG. 2. Note that the proportion ofoxygen atoms is not illustrated in FIG. 2.

In FIG. 2, dashed lines correspond to a line representing the atomicratio of [In]:[M]:[Zn]=(1+α):(1−α):1 (−1≤α≤1), a line representing theatomic ratio of [In]:[M]:[Zn]=(1+α):(1−α):2, a line representing theatomic ratio of [In]:[M]:[Zn]=(1+α):(1−α):3, a line representing theatomic ratio of [In]:[M]:[Zn]=(1+α):(1−α):4, and a line representing theatomic ratio of [In]:[M]:[Zn]=(1+α):(1−α):5.

Dashed-dotted lines correspond to a line representing the atomic ratioof [In]:[M]:[Zn]=1:1:β (β>0), a line representing the atomic ratio of[In]:[M]:[Zn]=1:2:β, a line representing the atomic ratio of[In]:[M]:[Zn]=1:3:β, a line representing the atomic ratio of[In]:[M]:[Zn]=1:4:β, a line representing the atomic ratio of[In]:[M]:[Zn]=1:7:β, a line representing the atomic ratio of[In]:[M]:[Zn]=2:1:β, and a line representing the atomic ratio of[In]:[M]:[Zn]=5:1:β.

An oxide semiconductor having the atomic ratio of [In]:[M]:[Zn]=0:2:1 ora neighborhood thereof in FIG. 2 tends to have a spinel crystalstructure.

Region A2 in FIG. 2 represents an example of a preferred range of atomicratios of indium to the element M and zinc contained in Region A1. Notethat Region A2 includes atomic ratios on a line representing the atomicratio of [In]:[M]:[Zn]=(1+γ):0:(1−γ)(−1≤γ≤1).

Region B2 in FIG. 2 represents an example of a preferred range of atomicratios of indium to the element M and zinc contained in Region B1. Notethat Region B2 includes atomic ratios from [In]:[M]:[Zn]=4:2:3 to[In]:[M]:[Zn]=4:2:4.1 and a neighborhood thereof. The neighborhoodincludes an atomic ratio of [In]:[M]:[Zn]=5:3:4. Region B2 includes anatomic ratio of [In]:[M]:[Zn]=5:1:6 and a neighborhood thereof.

Region A2 with high In concentrations provides higher conductivity thanRegion B2 and has a function of increasing carrier mobility of the oxidesemiconductor film (or field-effect mobility of a transistor).Therefore, the on-state current and carrier mobility of a transistorusing an oxide semiconductor film including Region A1 can be increased.

In contrast, Region B2 with low In concentrations provides lowerconductivity than Region A2 and has a function of decreasing leakagecurrent of the oxide semiconductor film or a transistor. Therefore, theoff-state current of a transistor using an oxide semiconductor filmincluding Region B1 can be decreased.

In the oxide semiconductor film of one embodiment of the presentinvention, Region A1 and Region B1 form a composite. That is, carriermovement occurs easily in Region A1, whereas carrier movement does notoccur easily in Region B1. Therefore, an oxide semiconductor of oneembodiment of the present invention can be used as a material with highcarrier mobility, excellent switching characteristics, and favorablesemiconductor characteristics.

In other words, Region A1 has a lower semiconductor property and higherconductivity than Region B1. Conversely, Region B1 has a highersemiconductor property and lower conductivity than Region A1. Here, ahigh semiconductor property means a wide band gap, favorable switchingcharacteristics, being close to an i-type semiconductor, or the like.

For example, a plurality of Regions A1 are present in particulate form(in cluster form) in the a-b plane direction and the c-axis direction asshown in FIGS. 1A and 1B. Note that clusters may be distributed unevenlyand irregularly. A plurality of clusters overlap with each other or areconnected to each other in some cases. For example, in some cases,shapes each including a cluster overlapping with another cluster areconnected to each other, so that Region A1 is observed to extend in acloud-like manner.

In other words, the clusters included in Region A1 have a lowersemiconductor property and higher conductivity than the clustersincluded in Region B1. Conversely, the clusters included in Region B1have a higher semiconductor property and lower conductivity than theclusters included in Region A1.

In other words, in the composite oxide semiconductor of one embodimentof the present invention, a first region with a high In concentrationand a second region with a low In concentration are connected in acloud-like manner. Alternatively, in the composite oxide semiconductorof one embodiment of the present invention, the first region where In isdistributed at a high concentration and the second region where In isnot distributed at a high concentration are connected in a cloud-likemanner.

As shown in FIGS. 1A and 1B, Regions A1 are connected to each other inthe a-b plane direction, so that Regions A1 can serve as a current path.Accordingly, the oxide semiconductor film can have increasedconductivity and a transistor using this oxide semiconductor film canhave increased field-effect mobility.

In other words, Regions B1 shown in FIGS. 1A and 1B are scattered inRegions A1. Therefore, Region B1 can exist in a state of beingsandwiched three-dimensionally by Regions A1. In other words, Region B1can exist in a state of being surrounded by Region A1. That is, RegionB1 is enclosed by Region A1.

From another perspective, Region B1 includes a cluster (also referred toas a second cluster) that is different from a cluster (also referred toas a first cluster) included in Region A1. In this structure, Region B1includes a plurality of second clusters and has a portion where theplurality of second clusters are connected to each other. In otherwords, the first cluster included in Region A1 includes a portion wherethe first cluster and another first cluster are connected to each otherin a cloud-like manner, and the second cluster included in Region B1includes a portion where the second cluster and another second clusterare connected to each other in a cloud-like manner.

Note that the proportion of scattered Regions A1 can be adjusted bychanging the formation conditions or composition of the composite oxidesemiconductor. For example, it is possible to form a composite oxidesemiconductor with a low proportion of Regions A1 or a composite oxidesemiconductor with a high proportion of Regions A1. In a composite oxidesemiconductor of one embodiment of the present invention, the proportionof Regions A1 is not always lower than that of Regions B1. In acomposite oxide semiconductor with an extremely high proportion ofRegions A1, depending on the observation range, Region B1 is sometimesformed in Region A1. The size of the particulate region of Region A1 canbe appropriately adjusted by changing, for example, the formationconditions or composition of the composite oxide semiconductor.

FIGS. 3A and 3B show a composite oxide semiconductor that has a lowerproportion of Regions A1 and a higher proportion of Regions B1 than thecomposite oxide semiconductor shown in FIGS. 1A and 1B.

FIGS. 4A and 4B show a composite oxide semiconductor that has a lowerproportion of Regions A1 and a higher proportion of Regions B1 than thecomposite oxide semiconductor shown in FIGS. 3A and 3B. Because of thelow proportion of Regions A1, the first clusters scattered withoutoverlapping with each other may be included as shown in FIGS. 4A and 4B.

Note that by changing the formation conditions or composition of thecomposite oxide semiconductor, it is possible to form a composite oxidesemiconductor that has a higher proportion of Regions A1 and a lowerproportion of Regions B1 than the composite oxide semiconductor shown inFIGS. 1A and 1B.

Here, when all of Regions A1 are connected in the a-b plane direction,the switching characteristics of a transistor deteriorate in some cases.For example, the off-state current of the transistor might increase. Itis thus preferable that as shown in FIGS. 3A and 3B and FIGS. 4A and 4B,Regions A1 be scattered in Regions B1. Therefore, Region A1 can exist ina state of being sandwiched three-dimensionally by Regions B1. In otherwords, Region A1 can exist in a state of being surrounded by Region B1.That is, Region A1 is enclosed by Region B1. As a result, the switchingcharacteristics of the transistor can be improved. Specifically, theoff-state current can be reduced.

In some cases, the boundary between Region A1 and Region B1 is notclearly observed. The sizes of Region A1 and Region B1 can be measuredwith energy dispersive X-ray spectroscopy (EDX) mapping images obtainedby EDX. For example, the diameter of a cluster in Region A1 is greaterthan or equal to 0.1 nm and less than or equal to 2.5 nm in the EDXmapping image of a cross-sectional photograph or a plan-view photographin some cases. Note that the diameter of the cluster is preferablygreater than or equal to 0.5 nm and less than or equal to 1.5 nm.

As described above, an oxide semiconductor of one embodiment of thepresent invention is a composite oxide semiconductor in which Region A1and Region B1 are mixed and have different functions that arecomplementary. For example, when an oxide semiconductor of oneembodiment of the present invention is an In—Ga—Zn oxide (hereinafterreferred to as IGZO), in which Ga is used as the element M, the oxidesemiconductor of one embodiment of the present invention can be calledcomplementary IGZO (abbreviation: C/IGZO).

In contrast, when Region A1 and Region B1 are stacked in a layeredmanner, for example, interaction does not take place or is unlikely totake place between Region A1 and Region B1, so that the function ofRegion A1 and that of Region B1 are independently performed in somecases. In that case, even when the carrier mobility is increased owingto Regions A1, the off-state current of the transistor might beincreased. Therefore, in the case where the above-described compositeoxide semiconductor or C/IGZO is used, a function of achieving highcarrier mobility and a function of achieving excellent switchingcharacteristics can be obtained at the same time. This is anadvantageous effect obtained by using a composite oxide semiconductor ofone embodiment of the present invention.

Note that in the case where the oxide semiconductor is deposited with asputtering apparatus, a film having an atomic ratio deviated from theatomic ratio of the target is formed. Especially for zinc, [Zn] in theatomic ratio of a deposited film is smaller than that in the atomicratio of the target in some cases depending on the substrate temperatureduring deposition.

The characteristics of the composite oxide semiconductor of oneembodiment of the present invention are not uniquely determined by theatomic ratio. Therefore, the illustrated regions represent preferredatomic ratios of Region A1 and Region B1 of the composite oxidesemiconductor; a boundary therebetween is not clear.

Here, Region B1 may have crystallinity. Region B1 preferably includes ac-axis aligned crystalline oxide semiconductor (CAAC-OS) describedlater. The CAAC-OS has c-axis alignment, its nanocrystals are connectedin the a-b plane direction, and its crystal structure has distortion.Note that the distortion in the CAAC-OS is a portion where the directionof a lattice arrangement changes between a region with a regular latticearrangement and another region with a regular lattice arrangement.

In FIG. 5A, a plurality of nanocrystals that are included in Region B1are schematically shown by dashed lines. The shape of the nanocrystal isbasically hexagon. However, the shape is not always a regular hexagonand is a non-regular hexagon in some cases. At the distorted portion, apolygonal nanocrystal such as a pentagonal nanocrystal or a heptagonalnanocrystal is included in some cases.

Note that a clear grain boundary cannot be observed even in the vicinityof the distorted portion in the CAAC-OS. That is, a lattice arrangementis distorted so that formation of a grain boundary is inhibited. This isprobably because the CAAC-OS can tolerate distortion owing to a lowdensity of arrangement of oxygen atoms in an a-b plane direction, theinteratomic bond distance changed by substitution of a metal element,and the like.

Furthermore, FIG. 5B schematically shows that nanocrystals have c-axisalignment and the c-axes are aligned in a direction substantiallyperpendicular to a surface over which the CAAC-OS film is formed (alsoreferred to as a formation surface) or the top surface of the CAAC-OSfilm. The CAAC-OS has a layered crystal structure (also referred to as alayered structure) having c-axis alignment and includes a layercontaining indium and oxygen (hereinafter referred to as an In layer)and a layer containing the element M, zinc, and oxygen (hereinafterreferred to as an (M,Zn) layer) that are stacked.

Note that indium and the element M are replaced with each other in somecases. Therefore, when some of the elements M in the (M,Zn) layer arereplaced with indium, the layer can also be referred to as an (In,M,Zn)layer. In that case, the In layer and the (In,M,Zn) layer are stacked inthe layered structure.

FIGS. 6A and 6B show an example in which the proportion of Regions A1 islow and the proportion of Regions B1 is high as compared to those inFIGS. 5A and 5B.

Oxide semiconductors have various structures and various properties. Anoxide semiconductor of one embodiment of the present invention may be acomposite oxide semiconductor including two or more of the amorphousoxide semiconductor, the polycrystalline oxide semiconductor, an a-likeOS described later, an nc-OS described later, and a CAAC-OS describedlater. Region A1 and Region B1 may have different crystallinities.

For example, Region A1 is preferably non-single-crystal. Note that inthe case where Region A1 has crystallinity, when Region A1 is formed ofindium, Region A1 tends to have a tetragonal crystal structure.Furthermore, when Region A1 is formed of indium oxide([In]:[M]:[Zn]=x:0:0 (x>0)), Region A1 tends to have a bixbyite crystalstructure. Furthermore, when Region A1 is formed of an In—Zn oxide([In]:[M]:[Zn]=x:0:z (x>0, z>0)), Region A1 tends to have a layeredcrystal structure.

For example, Region B1 is preferably non-single-crystal. Region B1preferably includes a CAAC-OS. Note that Region B1 does not necessarilyinclude only a CAAC-OS and may also include a region of apolycrystalline oxide semiconductor, an nc-OS, or the like.

The CAAC-OS is an oxide semiconductor with high crystallinity. Incontrast, in the CAAC-OS, a reduction in electron mobility due to agrain boundary is less likely to occur because a clear grain boundarycannot be observed. Entry of impurities, formation of defects, or thelike might decrease the crystallinity of an oxide semiconductor. Thismeans that the CAAC-OS has few impurities and defects (e.g., oxygenvacancies). Thus, with the CAAC-OS, a composite oxide semiconductor isphysically stable; thus, a composite oxide semiconductor which isresistant to heat and has high reliability can be provided.

<1-3. Transistor Including Oxide Semiconductor Film>

Next, the case where the above-described oxide semiconductor film isused for a transistor will be described.

With the use of the composite oxide semiconductor in a transistor, thetransistor can have high carrier mobility and high switchingcharacteristics. In addition, the transistor can have high reliability.

An oxide semiconductor film with low carrier density is preferably usedfor the transistor. For example, an oxide semiconductor film whosecarrier density is lower than 8×10¹¹/cm³, preferably lower than1×10¹¹/cm³, or further preferably lower than 1×10¹⁰/cm³, and greaterthan or equal to 1×10⁻⁹/cm³ is used as the oxide semiconductor film.

In order to reduce the carrier density of the oxide semiconductor film,the impurity concentration in the oxide semiconductor film is reduced sothat the density of defect states can be reduced. In this specificationand the like, a state with a low impurity concentration and a lowdensity of defect states is referred to as a highly purified intrinsicor substantially highly purified intrinsic state. A highly purifiedintrinsic or substantially highly purified intrinsic oxide semiconductorfilm has few carrier generation sources, and thus can have a low carrierdensity. A highly purified intrinsic or substantially highly purifiedintrinsic oxide semiconductor film has a low density of defect statesand accordingly has a low density of trap states in some cases.

Charges trapped by the trap states in the oxide semiconductor film takea long time to be released and may behave like fixed charges. Thus, thetransistor whose channel region is formed in the oxide semiconductorhaving a high density of trap states has unstable electricalcharacteristics in some cases.

To obtain stable electrical characteristics of the transistor, it iseffective to reduce the concentration of impurities in the oxidesemiconductor film. In order to reduce the concentration of impuritiesin the oxide semiconductor film, the concentration of impurities in afilm that is adjacent to the oxide semiconductor film is preferablyreduced. As examples of the impurities, hydrogen, nitrogen, alkalimetal, alkaline earth metal, iron, nickel, silicon, and the like aregiven.

Here, the influence of impurities in the oxide semiconductor film willbe described.

When silicon or carbon that is one of Group 14 elements is contained inthe oxide semiconductor film, defect states are formed. Thus, theconcentration of silicon or carbon in the oxide semiconductor and aroundan interface with the oxide semiconductor (measured by secondary ionmass spectrometry (SIMS)) is set lower than or equal to 2×10¹⁸atoms/cm³, and preferably lower than or equal to 2×10¹⁷ atoms/cm³.

When the oxide semiconductor film contains alkali metal or alkalineearth metal, defect states are formed and carriers are generated, insome cases. Thus, a transistor including an oxide semiconductor filmwhich contains alkali metal or alkaline earth metal is likely to benormally on. Therefore, it is preferable to reduce the concentration ofalkali metal or alkaline earth metal in the oxide semiconductor film.Specifically, the concentration of alkali metal or alkaline earth metalin the oxide semiconductor film measured by SIMS is set lower than orequal to 1×10¹⁸ atoms/cm³, and preferably lower than or equal to 2×10¹⁶atoms/cm³.

When the oxide semiconductor film contains nitrogen, the oxidesemiconductor film easily becomes n-type by generation of electronsserving as carriers and an increase of carrier density. Thus, atransistor whose semiconductor includes an oxide semiconductor thatcontains nitrogen is likely to be normally-on. For this reason, nitrogenin the oxide semiconductor is preferably reduced as much as possible;the nitrogen concentration measured by SIMS is set, for example, lowerthan 5×10¹⁹ atoms/cm³, preferably lower than or equal to 5×10¹⁸atoms/cm³, further preferably lower than or equal to 1×10¹⁸ atoms/cm³,and still further preferably lower than or equal to 5×10¹⁷ atoms/cm³.

Hydrogen contained in an oxide semiconductor film reacts with oxygenbonded to a metal atom to be water, and thus causes an oxygen vacancy(V_(o)), in some cases. Due to entry of hydrogen into the oxygen vacancy(V_(o)), an electron serving as a carrier is generated in some cases.Furthermore, in some cases, bonding of part of hydrogen to oxygen bondedto a metal atom causes generation of an electron serving as a carrier.Thus, a transistor including an oxide semiconductor which containshydrogen is likely to be normally on. Accordingly, it is preferable thathydrogen in the oxide semiconductor be reduced as much as possible.Specifically, the hydrogen concentration measured by SIMS in the oxidesemiconductor is lower than 1×10²⁰ atoms/cm³, preferably lower than1×10¹⁹ atoms/cm³, further preferably lower than 5×10¹⁸ atoms/cm³, andstill further preferably lower than 1×10¹⁸ atoms/cm³.

The oxygen vacancies (V_(o)) in the oxide semiconductor film can bereduced by introduction of oxygen into the oxide semiconductor film.That is, the oxygen vacancies (V_(o)) in the oxide semiconductor filmdisappear when the oxygen vacancies (V_(o)) are filled with oxygen.Accordingly, diffusion of oxygen in the oxide semiconductor film canreduce the oxygen vacancies (V_(o)) in a transistor and improve thereliability of the transistor.

As a method for introducing oxygen into the oxide semiconductor film,for example, an oxide in which oxygen content is higher than that in thestoichiometric composition is provided in contact with the oxidesemiconductor film. That is, in the oxide, a region including oxygen inexcess of that in the stoichiometric composition (hereinafter alsoreferred to as an excess oxygen region) is preferably formed. Inparticular, in the case of using an oxide semiconductor film in atransistor, an oxide including an excess oxygen region is provided in abase film, an interlayer film, or the like in the vicinity of thetransistor, whereby oxygen vacancies in the transistor are reduced, andthe reliability can be improved.

When an oxide semiconductor film with sufficiently reduced impurityconcentration is used for a channel formation region in a transistor,the transistor can have stable electrical characteristics.

One embodiment of the present invention is a semiconductor deviceincluding a transistor. The transistor includes a first gate electrode,a first insulating film over the first gate electrode, an oxidesemiconductor film over the first insulating film, a second insulatingfilm over the oxide semiconductor film, a second gate electrode over thesecond insulating film, and a third insulating film over the oxidesemiconductor film and the second gate electrode. The oxidesemiconductor film includes a channel region overlapping with the firstor second gate electrode, a source region in contact with the thirdinsulating film, and a drain region in contact with the third insulatingfilm. The first gate electrode and the second gate electrode areelectrically connected to each other.

The above transistor includes, in terms of its electricalcharacteristics, a first region where the maximum value of thefield-effect mobility of the transistor at a gate voltage of higher than0 V and lower than or equal to 10 V is larger than or equal to 10 cm²/Vsand smaller than 200 cm²/Vs, a second region where the threshold voltageis higher than or equal to −1 V and lower than or equal to 1 V, a thirdregion where the S value is smaller than 0.3 V/decade, and a fourthregion where the off-state current is lower than 1×10⁻¹² A/cm².Furthermore, μ_(FE)(max)/μ_(FE)(V_(g)=2V) is larger than or equal to 1and smaller than 10 where μ_(FE)(max) represents the maximum value ofthe field-effect mobility of the transistor and μ_(FE)(V_(g)=2V)represents the value of the field-effect mobility of the transistor at agate voltage of 2 V.

Preferably, the above transistor includes, in terms of its electricalcharacteristics, a first region where the maximum value of thefield-effect mobility of the transistor at a gate voltage of higher than0 V and lower than or equal to 10 V is larger than or equal to 60 cm²/Vsand smaller than 200 cm²/Vs, a second region where the threshold voltageis higher than or equal to −1 V and lower than or equal to 1 V, a thirdregion where the S value is smaller than 0.3 V/decade, and a fourthregion where the off-state current is lower than 1×10⁻¹² A/cm².Furthermore, μ_(FE)(max)/μ_(FE)(V_(g)=2V) is larger than or equal to 1and smaller than 2 where μ_(FE)(max) represents the maximum value of thefield-effect mobility of the transistor and μ_(FE)(V_(g)=2V) representsthe value of the field-effect mobility of the transistor at a gatevoltage of 2 V.

In other words, the semiconductor device of one embodiment of thepresent invention is a transistor which includes an oxide semiconductorfilm in its channel region and whose field-effect mobility, thresholdvoltage, off-state current, and S value are extremely favorable. Such asemiconductor device can be favorably used as a transistor in a pixel ofa liquid crystal display or an organic EL display or a transistor in adriver circuit of a liquid crystal display or an organic EL display, forexample.

<1-4. Method for Manufacturing Composite Oxide Semiconductor>

An example of a method for manufacturing the composite oxidesemiconductor shown in FIGS. 1A and 1B and other drawings is described.A composite oxide semiconductor of one embodiment of the presentinvention can be formed with a sputtering apparatus.

[Sputtering Apparatus]

FIG. 7A is a cross-sectional view of a deposition chamber 2501 of thesputtering apparatus. FIG. 7B is a plan view of a magnet unit 2530 a anda magnet unit 2530 b of the sputtering apparatus.

The deposition chamber 2501 illustrated in FIG. 7A includes a targetholder 2520 a, a target holder 2520 b, a backing plate 2510 a, a backingplate 2510 b, a target 2502 a, a target 2502 b, a member 2542, and asubstrate holder 2570. Note that the target 2502 a is placed over thebacking plate 2510 a. The backing plate 2510 a is placed over the targetholder 2520 a. The magnet unit 2530 a is placed under the target 2502 awith the backing plate 2510 a therebetween. The target 2502 b is placedover the backing plate 2510 b. The backing plate 2510 b is placed overthe target holder 2520 b. The magnet unit 2530 b is placed under thetarget 2502 b with the backing plate 2510 b therebetween.

As illustrated in FIGS. 7A and 7B, the magnet unit 2530 a includes amagnet 2530N1, a magnet 2530N2, a magnet 2530S, and a magnet holder2532. The magnet 2530N1, the magnet 2530N2, and the magnet 2530S areplaced over the magnet holder 2532 in the magnet unit 2530 a. The magnet2530N1, the magnet 2530N2, and the magnet 2530S are spaced. Note thatthe magnet unit 2530 b has a structure similar to that of the magnetunit 2530 a. When the substrate 2560 is transferred into the depositionchamber 2501, the substrate 2560 is placed in contact with the substrateholder 2570.

The target 2502 a, the backing plate 2510 a, and the target holder 2520a are separated from the target 2502 b, the backing plate 2510 b, andthe target holder 2520 b by the member 2542. Note that the member 2542is preferably an insulator. The member 2542 may be a conductor or asemiconductor. The member 2542 may be a conductor or a semiconductorwhose surface is covered with an insulator.

The target holder 2520 a and the backing plate 2510 a are fixed to eachother with a screw (e.g., a bolt) and have the same potential. Thetarget holder 2520 a has a function of supporting the target 2502 a withthe backing plate 2510 a positioned therebetween. The target holder 2520b and the backing plate 2510 b are fixed to each other with a screw(e.g., a bolt) and have the same potential. The target holder 2520 b hasa function of supporting the target 2502 b with the backing plate 2510 bpositioned therebetween.

The backing plate 2510 a has a function of fixing the target 2502 a. Thebacking plate 2510 b has a function of fixing the target 2502 b.

Magnetic lines of force 2580 a and 2580 b formed by the magnet unit 2530a are illustrated in FIG. 7A.

As illustrated in FIG. 7B, the magnet unit 2530 a has a structure inwhich the magnet 2530N1 having a rectangular or substantiallyrectangular shape, the magnet 2530N2 having a rectangular orsubstantially rectangular shape, and the magnet 2530S having arectangular or substantially rectangular shape are fixed to the magnetholder 2532. The magnet unit 2530 a can be oscillated horizontally asshown by an arrow in FIG. 7B. For example, the magnet unit 2530 a may beoscillated with a beat of greater than or equal to 0.1 Hz and less thanor equal to 1 kHz.

The magnetic field over the target 2502 a changes in accordance withoscillation of the magnet unit 2530 a. The region with an intensemagnetic field is a high-density plasma region; thus, sputtering of thetarget 2502 a easily occurs in the vicinity of the region. The sameapplies to the magnet unit 2530 b.

<1-5. Manufacturing Flow of Composite Oxide Semiconductor>

FIG. 8 is a process flow chart showing a method for manufacturing acomposite oxide semiconductor.

The composite oxide semiconductor shown in FIGS. 1A and 1B ismanufactured through at least first to fourth processes shown in FIG. 8.

[First Process: Process of Placing Substrate in Deposition Chamber]

The first process includes a step of placing a substrate in a depositionchamber (see Step S101 in FIG. 8).

In the first process, for example, the substrate 2560 is placed on thesubstrate holder 2570 of the deposition chamber 2501 shown in FIGS. 7Aand 7B.

The temperature of the substrate 2560 in deposition influences theelectrical properties of a composite oxide semiconductor. The higher thesubstrate temperature is, the higher the crystallinity and reliabilityof the composite oxide semiconductor can be. In contrast, the lower thesubstrate temperature is, the lower the crystallinity of the compositeoxide semiconductor can be and the higher the carrier mobility thereofcan be. In particular, the lower the substrate temperature in depositionis, the more the field-effect mobility at a low gate voltage (e.g.,higher than 0 V and lower than or equal to 2 V) is notably increased ina transistor including the composite oxide semiconductor.

The temperature of the substrate 2560 can be set higher than or equal toroom temperature (25° C.) and lower than or equal to 200° C., preferablyhigher than or equal to room temperature and lower than or equal to 170°C., further preferably higher than or equal to room temperature andlower than or equal to 130° C. The substrate temperature in the aboverange is suitable for the case of using a large glass substrate (e.g., aglass substrate having a size of the 8th generation or the 10thgeneration described later). In particular, when the substratetemperature in deposition of a composite oxide semiconductor is roomtemperature, i.e., the substrate is not heated intentionally, thesubstrate can be favorably prevented from bending or warping.

The substrate 2560 may be cooled with a cooling mechanism or the likeprovided for the substrate holder 2570.

In the case where the temperature of the substrate 2560 is set higherthan or equal to 100° C. and lower than or equal to 130° C., water inthe composite oxide semiconductor can be removed. Water as an impurityis removed in this manner, whereby the field-effect mobility and thereliability can be improved at the same time.

Furthermore, in the case where the temperature of the substrate 2560 isset higher than or equal to 100° C. and lower than or equal to 130° C.,the sputtering apparatus can be prevented from warping due to overheat.Accordingly, semiconductor devices can be manufactured with higherproductivity. The productivity is thus stabilized, so that a large-scaleproduction apparatus is easy to employ. Thus, a large display deviceincluding a large substrate can be easily manufactured.

When the temperature of the substrate 2560 is high, water in thecomposite oxide semiconductor can be more effectively removed andmoreover, the composite oxide semiconductor can have increasedcrystallinity. For example, the temperature of the substrate 2560 is setto higher than or equal to 80° C. and lower than or equal to 200° C.,preferably higher than or equal to 100° C. and lower than or equal to170° C., whereby a composite oxide semiconductor with high crystallinitycan be formed.

[Second Process: Process of Introducing Gas into Deposition Chamber]

The second process includes a step of introducing a gas into thedeposition chamber (see Step S201 in FIG. 8).

In the second process, for example, a gas is introduced into thedeposition chamber 2501 in FIGS. 7A and 7B. One or both of an argon gasand an oxygen gas are introduced as the gas. Note that instead of anargon gas, an inert gas such as helium, xenon, or krypton can be used.

The proportion of oxygen in the whole deposition gas in forming acomposite oxide semiconductor using an oxygen gas is referred to as anoxygen flow rate percentage in some cases.

The higher the oxygen flow rate percentage is, the higher thecrystallinity and reliability of the composite oxide semiconductor canbe. In contrast, the lower the oxygen flow rate percentage is, the lowerthe crystallinity of the composite oxide semiconductor can be and thehigher the carrier mobility thereof can be. In particular, the lower theoxygen flow rate percentage is, the more the field-effect mobility at alow gate voltage (e.g., higher than 0 V and lower than or equal to 2 V)is notably increased in a transistor including the composite oxidesemiconductor.

The oxygen flow rate percentage can be appropriately set in the rangefrom 0% to 100% inclusive so that favorable characteristics of thecomposite oxide semiconductor suitable to the uses can be obtained.

For example, in the case where the composite oxide semiconductor is usedfor a semiconductor layer of a transistor having high field-effectmobility, the oxygen flow rate percentage is set to higher than 0% andlower than or equal to 30%, preferably higher than or equal to 5% andlower than or equal to 30%, further preferably higher than or equal to7% and lower than or equal to 15% in deposition of the composite oxidesemiconductor. Alternatively, the composite oxide semiconductor may beformed without using an oxygen gas, in which case the oxygen flow ratepercentage is 0%.

To make both the field-effect mobility and reliability of a transistorrelatively high, the oxygen flow rate percentage in deposition of thecomposite oxide semiconductor is set to higher than 30% and lower than70%, preferably higher than 30% and lower than or equal to 50%.Alternatively, the oxygen flow rate percentage in deposition of thecomposite oxide semiconductor is set to higher than or equal to 10% andlower than or equal to 50%, preferably higher than or equal to 30% andlower than or equal to 50%.

To make the reliability of a transistor high, the oxygen flow ratepercentage in deposition of the composite oxide semiconductor is set tohigher than or equal to 70% and lower than or equal to 100%.

When the substrate temperature and the oxygen flow rate percentage indeposition are controlled in this manner, a composite oxidesemiconductor that provides desired electrical characteristics can bedeposited. For example, a reduction (an increase) of substratetemperature and a reduction (an increase) of oxygen flow rate percentagecontribute to the field-effect mobility to the same degree, in somecases. Therefore, even when the substrate temperature cannot beincreased sufficiently with the constraints of an apparatus, forexample, a transistor having field-effect mobility substantially thesame as that when the substrate temperature is increased can be obtainedby increasing the oxygen flow rate percentage.

Note that even when a composite oxide semiconductor whose carriermobility is increased by control of the substrate temperature and oxygenflow rate percentage in deposition is used, a transistor with highreliability can be obtained by reducing oxygen vacancies and impuritiesby a method described later.

In addition, increasing the purity of the gas is necessary. For example,as an oxygen gas or an argon gas used as the gas, a gas which is highlypurified to have a dew point of −40° C. or lower, preferably −80° C. orlower, further preferably −100° C. or lower, still further preferably−120° C. or lower is used, whereby entry of moisture or the like intothe composite oxide semiconductor can be minimized.

The deposition chamber 2501 is preferably evacuated to high vacuum(about 5×10⁻⁷ Pa to 1×10⁻⁴ Pa) with an entrapment vacuum evacuation pumpsuch as a cryopump so that water or the like, which is an impurity forthe composite oxide semiconductor, is removed as much as possible. Inparticular, the partial pressure of gas molecules corresponding to H₂O(gas molecules corresponding to m/z=18) in the deposition chamber 2501in the standby mode of the sputtering apparatus is preferably lower thanor equal to 1×10⁻⁴ Pa, further preferably lower than or equal to 5×10⁻⁵Pa.

[Third Process: Process of Applying Voltage to Target]

The third process includes a step of applying voltage to a target (seeStep S301 in FIG. 8).

In the third process, for example, voltage is applied to the targetholder 2520 a and the target holder 2520 b in FIGS. 7A and 7B. As anexample, a potential applied to a terminal V1 connected to the targetholder 2520 a is lower than a potential applied to a terminal V2connected to the substrate holder 2570. A potential applied to aterminal V4 connected to the target holder 2520 b is lower than thepotential applied to the terminal V2 connected to the substrate holder2570. The potential applied to the terminal V2 connected to thesubstrate holder 2570 is a ground potential. A potential applied to aterminal V3 connected to the magnet holder 2532 is a ground potential.

Note that the potentials applied to the terminals V1, V2, V3, and V4 arenot limited to the above potentials. Not all the target holder 2520, thesubstrate holder 2570, and the magnet holder 2532 are necessarilysupplied with potentials. For example, the substrate holder 2570 may beelectrically floating. Note that it is assumed that a power sourcecapable of controlling a potential applied to the terminal V1 iselectrically connected to the terminal V1. As the power source, a DCpower source, an AC power source, or an RF power source may be used.

As the target 2502 a and the target 2502 b, a target including indium,the element M (M is Al, Ga, Y, or Sn), zinc, and oxygen is preferablyused. For example, an In—Ga—Zn metal oxide target (In:Ga:Zn=4:2:4.1[atomic ratio]) or an In—Ga—Zn metal oxide target (In:Ga:Zn=5:1:7[atomic ratio]) can be used as the target 2502 a and the target 2502 b.In the following description, the case of using an In—Ga—Zn metal oxidetarget (In:Ga:Zn=4:2:4.1 [atomic ratio]) is described.

[Fourth Process: Process of Depositing Composite Oxide Semiconductor onSubstrate]

The fourth process includes a step in which sputtered particles areejected from the target and a composite oxide semiconductor is depositedon the substrate (see Step S401 in FIG. 8).

In the fourth process, for example, in the deposition chamber 2501illustrated in FIGS. 7A and 7B, an argon gas or an oxygen gas is ionizedto be separated into cations and electrons, and plasma is created. Then,the cations in the plasma are accelerated toward the targets 2502 a and2502 b by the potentials applied to the target holders 2520 a and 2520b. Sputtered particles are generated when the cations collide with theIn—Ga—Zn metal oxide target, and the sputtered particles are depositedon the substrate 2560.

Note that in an In—Ga—Zn metal oxide target with an atomic ratio ofIn:Ga:Zn=4:2:4.1 or 5:1:7 that is used as the targets 2502 a and 2502 b,a plurality of crystal grains with different compositions are includedin some cases. In most cases, for example, the diameters of theplurality of crystal grains are each 10 μm or less. In the case where,for example, crystal grains with a high proportion of In are included inthe In—Ga—Zn metal oxide target, the proportion of Region A1 describedabove is increased in some cases.

<1-6. Deposition Model>

In the fourth process, a deposition model shown in FIGS. 9A to 9C can bepresumed.

FIGS. 9A to 9C are schematic cross-sectional views of the vicinity ofthe target 2502 a shown in FIGS. 7A and 7B. Note that FIG. 9A shows thestate of the target before use, FIG. 9B shows the state of the targetbefore deposition, and FIG. 9C shows the state of the target during thedeposition. Note that in FIGS. 9A to 9C, the target 2502 a, plasma 2190,a cation 2192, sputtered particles 2504 a and 2506 a, and the like areshown.

In FIG. 9A, a surface of the target 2502 a is relatively flat and itscomposition (e.g., the composition ratio between In, Ga, and Zn) isuniform. In contrast, in FIG. 9B, unevenness is formed and compositionalsegregation occurs on the surface of the target 2502 a by sputteringperformed in advance or the like. The unevenness and the segregation canoccur because of plasma (e.g., Ar plasma) generated in the sputteringperformed in advance. Note that FIG. 9B illustrates a segregation region2504 and a segregation region 2506. Here, the segregation region 2504 isa region containing a large amount of Ga and a large amount of Zn (aGa,Zn-rich region), and the segregation region 2506 is a regioncontaining a large amount of In (an In-rich region). The segregationregion 2504, which contains a large amount of Ga, is formed because themelting point of Ga lower than that of In allows part of Ga to be meltedby heat applied to the target 2502 a during the plasma treatment andaggregate.

[First Step]

In FIG. 9C, an argon gas or an oxygen gas is ionized and separated intothe cations 2192 and electrons (not illustrated), and the plasma 2190 isgenerated. After that, the cations 2192 in the plasma 2190 areaccelerated toward the target 2500 a (here, an In—Ga—Zn oxide target).The cations 2192 collide with the In—Ga—Zn oxide target, whereby thesputtered particles 2504 a and 2506 a are generated and ejected from theIn—Ga—Zn oxide target. Note that since the sputtered particles 2504 aare ejected from the segregation region 2504, they form a Ga,Zn-richcluster in some cases. Since the sputtered particles 2506 a are ejectedfrom the segregation region 2506, they form an In-rich cluster in somecases.

When an In—Ga—Zn oxide target is used, presumably, the sputteredparticles 2504 a are preferentially sputtered first from the segregationregion 2504. This is because Ga and Zn, which have lower relative atomicmasses than In, are preferentially ejected from the In—Ga—Zn oxidetarget by collision of the cation 2192 with the In—Ga—Zn oxide target.The sputtered particles 2504 a that are ejected are deposited over thesubstrate, thereby forming Region B1 illustrated in FIGS. 1A and 1B andother drawings.

[Second Step]

Next, as illustrated in FIG. 9C, the sputtered particles 2506 a aresputtered from the segregation region 2506. The sputtered particles 2506a collide with Region B1 that has been formed over the substrate,thereby forming Region A1 illustrated in FIGS. 1A and 1B and otherdrawings.

As illustrated in FIG. 9C, the target 2502 a is subjected to sputteringthroughout the deposition; thus, generation of the segregation region2504 and disappearance of the segregation region 2504 occurintermittently.

The deposition model including the first step and the second step isrepeated, whereby the composite oxide semiconductor that is oneembodiment of the present invention and shown in FIGS. 1A and 1B andother drawings can be obtained.

That is, the sputtered particles (2506 a and 2504 a) are respectivelyejected from the In-rich segregation region 2506 and the Ga,Zn-richsegregation region 2504 to be deposited over the substrate. The In-richregions are connected to each other in a cloud-like manner over thesubstrate, so that a composite oxide semiconductor of one embodiment ofthe present invention as illustrated in FIGS. 1A and 1B can be formed.In a film of the composite oxide semiconductor, the In-rich regions areconnected to each other in a cloud-like manner. Thanks to this, atransistor using the composite oxide semiconductor has a high on-statecurrent (I_(on)) and high field-effect mobility (μFE).

In this manner, for a transistor having a high on-state current (I_(on))and high field-effect mobility (μFE), In is of importance and othermetals (e.g., Ga) are not always necessary.

Note that described above as an example is a model in which a compositeoxide semiconductor of one embodiment of the present invention is formedwith the use of an argon gas. In that case, the composite oxidesemiconductor might contain many oxygen vacancies. When the compositeoxide semiconductor contains many oxygen vacancies, shallow defectstates (also referred to as sDOS) are formed in the composite oxidesemiconductor in some cases. When sDOS is formed in the composite oxidesemiconductor, the sDOS serves as a carrier trap, resulting in areduction in on-state current and field-effect mobility.

Therefore, when a composite oxide semiconductor is formed with the useof an argon gas, it is preferable to supply oxygen into the compositeoxide semiconductor after formation thereof so that oxygen vacancies inthe composite oxide semiconductor are compensated and sDOS is reduced.

Such oxygen supply can be conducted by, for example, performing heattreatment in an atmosphere that contains oxygen after the formation ofthe composite oxide semiconductor, or performing plasma treatment in anatmosphere that contains oxygen. Alternatively, either an insulatingfilm that is in contact with the composite oxide semiconductor of oneembodiment of the present invention or an insulating film in thevicinity of the composite oxide semiconductor is made to contain excessoxygen. Details of the mode in which such an insulating film containsexcess oxygen are described in Embodiment 2.

Note that the formation method is not limited to a sputtering method; apulsed laser deposition (PLD) method, a plasma-enhanced chemical vapordeposition (PECVD) method, a thermal chemical vapor deposition (CVD)method, an atomic layer deposition (ALD) method, a vacuum evaporationmethod, or the like may be used. As an example of a thermal CVD method,a metal organic chemical vapor deposition (MOCVD) method can be given.

<1-7. Examination of Deposition Model>

Next, to examine the above-described deposition model, the shape of thesurface of the sputtering target and distributions of the compositionsover the surface were examined. Here, a change in the sputtering targetbefore and after the sputtering was examined.

FIG. 10 illustrates fabrication of a sample and an analysis method.

For the sample, a part that is cut from a metal oxide target was used.Here, four kinds of targets were used: a metal oxide target in which theatomic ratio between the metal elements is In:Ga:Zn=4:2:3, a metal oxidetarget in which the atomic ratio between the metal elements isIn:Ga:Zn=1:1:1, a metal oxide target in which the atomic ratio betweenthe metal elements is In:Ga:Zn=5:1:6, and a metal oxide target in whichthe atomic ratio between the metal elements is In:Ga:Zn=5:1:8.

Next, a surface of the sample was polished. Then, the polished surfacewas observed with a scanning electron microscope (SEM) and analyzed byenergy dispersive X-ray spectroscopy (SEM-EDX) with regard to thecomposition. The SEM observation and EDX measurement were performed withEX-370 produced by HORIBA, Ltd. at an acceleration voltage of 15 kV.

Next, sputtering was performed on the sample surface. The sputtering wasperformed for one hour using an argon gas as a deposition gas under apressure of 0.4 Pa and with a DC power of 200 W.

The surface subjected to the sputtering was observed with a SEM andanalyzed by SEM-EDX with regard to the composition in theabove-described manner.

In the analysis by EDX, an EDX spectrum of a point is obtained in such amanner that electron beam irradiation is performed on the point in ananalysis target region of a sample, and the energy of characteristicX-rays of the sample generated by the irradiation and its frequency aremeasured. Here, peaks of an EDX spectrum of the point were attributed toelectron transition to the L shell in an In atom, electron transition tothe L shell in a Ga atom, and electron transition to the L shell in a Znatom and the K shell in an O atom, and the proportions of the atoms inthe point were calculated. An EDX mapping image indicating distributionsof the proportions of the atoms can be obtained through the process inan analysis target region of a sample.

First, SEM images and EDX mapping images of the metal oxide target witha ratio of In:Ga:Zn=4:2:3 are shown in FIG. 11 and FIG. 12. FIG. 11shows the SEM image and EDX mapping images of the sample surface beforethe sputtering and FIG. 12 shows the SEM image and EDX mapping images ofthe sample surface after the sputtering. In each of FIG. 11 and FIG. 12,the EDX mapping images of O atoms, Zn atoms, Ga atoms, and In atomsexisting in the range of the SEM image are shown.

As can be seen from FIG. 11, although voids (holes) are observed in theSEM image, the sample surface is relatively flat. In addition, aplurality of grains are observed in the SEM image and it is shown thatthe sample is polycrystalline. Although the EDX mapping image showsZn-rich regions in some parts, it was found that the distribution ofeach element is substantially uniform.

Meanwhile, as shown in FIG. 12, it was found that the sputtering formedunevenness on the sample surface. Specifically, a particulateprecipitate with a diameter of approximately greater than or equal to0.1 μm and less than or equal to 5 μm was observed on the samplesurface. Note that in the EDX mapping images in FIG. 12, there arepoints the EDX spectra of which were not obtained owing to the influenceof the unevenness on the surface.

The EDX mapping images in FIG. 12 show that the O atoms, the Zn atoms,and the Ga atoms have distribution reflecting the shape of the samplesurface and their proportions vary widely from part to part. Moreover,it is shown that the proportions of the Ga atoms and the Zn atoms tendto be high on the surface of the precipitate. In contrast, thedistribution of the In atoms does not reflect the shape of the samplesurface and the In atoms are more uniformly distributed than otheratoms.

FIGS. 13A and 13B show pie graphs showing the ratios between In, Ga, andZn in some positions. In FIG. 14, the results in FIGS. 13A and 13B areshown in the form of column graphs. As shown in FIGS. 13A and 13B andFIG. 14, the composition ratio is substantially uniform before thesputtering and is substantially the same as that of the target; however,after the sputtering, the composition ratio varies from position toposition. Specifically, it was found that the precipitate observed afterthe sputtering included a region where the amount of In is small and Gaand Zn were segregated.

SEM images and EDX mapping images of the metal oxide target with a ratioof In:Ga:Zn=1:1:1 are shown in FIG. 15 and FIG. 16. SEM images and EDXmapping images of the metal oxide target with a ratio of In:Ga:Zn=5:1:6are shown in FIG. 17 and FIG. 18. SEM images and EDX mapping images ofthe metal oxide target with a ratio of In:Ga:Zn=5:1:8 are shown in FIG.19 and FIG. 20.

As described above, in any of the cases of the metal oxide targets withdifferent composition ratios, a precipitate having a low proportion ofIn and high proportions of Ga and Zn exists on the surface after thesputtering. It was also shown that In is distributed more uniformly thanO, Ga, and Zn.

The above results show that a segregation region that contains a largeamount of Ga and a large amount of Zn is formed on the surface of themetal oxide target by the sputtering. It is also found that In isuniformly distributed. This indicates that the above deposition model isquite appropriate.

<1-8. Classification of Oxide Semiconductor>

Next, classification of oxide semiconductors is described.

Oxide semiconductors are classified into a single crystal oxidesemiconductor and a non-single-crystal oxide semiconductor. Examples ofthe non-single-crystal oxide semiconductor include a c-axis alignedcrystalline oxide semiconductor (CAAC-OS), a polycrystalline oxidesemiconductor, a nanocrystalline oxide semiconductor (nc-OS), anamorphous-like oxide semiconductor (a-like OS), and an amorphous oxidesemiconductor.

From another perspective, oxide semiconductors are classified into anamorphous oxide semiconductor and a crystalline oxide semiconductor.Examples of the crystalline oxide semiconductor include a single crystaloxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor,and an nc-OS.

An amorphous structure is generally thought to be isotropic and have nonon-uniform structure, to be metastable and have no fixed atomicarrangement, to have a flexible bond angle, and to have a short-rangeorder but have no long-range order, for example.

In other words, a stable oxide semiconductor cannot be regarded as acompletely amorphous oxide semiconductor. Moreover, an oxidesemiconductor that is not isotropic (e.g., an oxide semiconductor thathas a periodic structure in a microscopic region) cannot be regarded asa completely amorphous oxide semiconductor. In contrast, an a-like OS,which is not isotropic, has an unstable structure that contains a void.Because of its instability, an a-like OS has physical properties similarto those of an amorphous oxide semiconductor.

[CAAC-OS]

First, a CAAC-OS is described.

A CAAC-OS is one of oxide semiconductors and has a plurality of c-axisaligned crystal parts (also referred to as pellets).

The CAAC-OS is an oxide semiconductor with high crystallinity. Entry ofimpurities, formation of defects, or the like might decrease thecrystallinity of an oxide semiconductor. This means that the CAAC-OS hasfew impurities and defects (e.g., oxygen vacancies).

Note that an impurity means an element other than the main components ofan oxide semiconductor, such as hydrogen, carbon, silicon, or atransition metal element. For example, an element (specifically, siliconor the like) having higher strength of bonding to oxygen than a metalelement included in an oxide semiconductor extracts oxygen from theoxide semiconductor, which results in disorder of the atomic arrangementand reduced crystallinity of the oxide semiconductor. A heavy metal suchas iron or nickel, argon, carbon dioxide, or the like has a large atomicradius (or molecular radius), and thus disturbs the atomic arrangementof the oxide semiconductor and decreases crystallinity.

[nc-OS]

Next, an nc-OS is described.

Analysis of an nc-OS by XRD is described. When the structure of an nc-OSis analyzed by an out-of-plane method, a peak indicating orientationdoes not appear. That is, a crystal of an nc-OS does not haveorientation.

The nc-OS is an oxide semiconductor that has higher regularity than anamorphous oxide semiconductor. Thus, the nc-OS has a lower density ofdefect states than the a-like OS and the amorphous oxide semiconductor.Note that there is no regularity of crystal orientation betweendifferent pellets in the nc-OS. Therefore, the nc-OS has a higherdensity of defect states than the CAAC-OS in some cases.

[A-Like OS]

An a-like OS has a structure between the structure of an nc-OS and thestructure of an amorphous oxide semiconductor.

The a-like OS contains a void or a low-density region. The a-like OS hasan unstable structure because it contains a void.

The a-like OS has a lower density than the nc-OS and the CAAC-OS becauseit contains a void. Specifically, the density of the a-like OS is higherthan or equal to 78.6% and lower than 92.3% of the density of the singlecrystal oxide semiconductor having the same composition. The density ofthe nc-OS and the density of the CAAC-OS are each higher than or equalto 92.3% and lower than 100% of the density of the single crystal oxidesemiconductor having the same composition. It is difficult to deposit anoxide semiconductor having a density lower than 78% of the density ofthe single crystal oxide semiconductor.

For example, in the case of an oxide semiconductor whose atomic ratio ofIn to Ga and Zn is 1:1:1, the density of single crystal InGaZnO₄ with arhombohedral crystal structure is 6.357 g/cm³. Accordingly, in the caseof the oxide semiconductor whose atomic ratio of In to Ga and Zn is1:1:1, the density of the a-like OS is higher than or equal to 5.0 g/cm³and lower than 5.9 g/cm³, for example. In the case of the oxidesemiconductor whose atomic ratio of In to Ga and Zn is 1:1:1, thedensity of the nc-OS and the density of the CAAC-OS are each higher thanor equal to 5.9 g/cm³ and lower than 6.3 g/cm³, for example.

In the case where an oxide semiconductor having a certain compositiondoes not exist in a single crystal state, single crystal oxidesemiconductors with different compositions are combined at an adequateratio, which makes it possible to calculate a density equivalent to thatof a single crystal oxide semiconductor with the desired composition.The density of a single crystal oxide semiconductor having the desiredcomposition may be calculated using a weighted average with respect tothe combination ratio of the single crystal oxide semiconductors withdifferent compositions. Note that it is preferable to use as few kindsof single crystal oxide semiconductors as possible to calculate thedensity.

As described above, oxide semiconductors have various structures andvarious properties. In the oxide semiconductor film of one embodiment ofthe present invention, two or more of an amorphous oxide semiconductor,an a-like OS, an nc-OS, and a CAAC-OS may be mixed.

Note that Region A1 described above is preferably non-single-crystal.Region B1 is preferably non-single-crystal. Region A1 and Region B1 mayhave different crystallinities.

At least part of this embodiment can be implemented in combination withany of the other embodiments described in this specification asappropriate.

Embodiment 2

In this embodiment, a transistor in a mode different from that of thetransistor in Embodiment 1 is described with reference to FIGS. 21A to21C, FIG. 22, FIGS. 23A and 23B, FIGS. 24A and 24B, FIGS. 25A and 25B,FIGS. 26A and 26B, FIGS. 27A and 27B, FIGS. 28A and 28B, FIGS. 29A and29B, FIGS. 30A and 30B, FIGS. 31A to 31C, FIGS. 32A to 32C, FIGS. 33A to33C, FIGS. 34A to 34C, FIGS. 35A to 35C, FIGS. 36A and 36B, FIGS. 37Aand 37B, and FIGS. 38A to 38C.

<2-1. Structure Example of Transistor>

Structures of a transistor of one embodiment of the present inventionare described.

Structure Example 1 of Transistor

FIG. 21A is a top view of a transistor 100A. FIG. 21B is across-sectional view taken along dashed-dotted line X1-X2 in FIG. 21A.FIG. 21C is a cross-sectional view taken along dashed-dotted line Y1-Y2in FIG. 21A. For clarity, some components such as an insulating film 110are not illustrated in FIG. 21A. As in FIG. 21A, some components are notillustrated in some cases in top views of transistors described below.In addition, the direction of dashed-dotted line X1-X2 may be referredto as the channel length (L) direction, and the direction ofdashed-dotted line Y1-Y2 may be referred to as the channel width (W)direction.

The transistor 100A illustrated in FIGS. 21A to 21C includes aconductive film 106 over a substrate 102, an insulating film 104 overthe conductive film 106, an oxide semiconductor film 108 over theinsulating film 104, the insulating film 110 over the oxidesemiconductor film 108, a conductive film 112 over the insulating film110, and an insulating film 116 over the insulating film 104, the oxidesemiconductor film 108, and the conductive film 112. The oxidesemiconductor film 108 includes a channel region 108 i overlapping withthe conductive film 112, a source region 108 s in contact with theinsulating film 116, and a drain region 108 d in contact with theinsulating film 116.

The insulating film 116 contains nitrogen or hydrogen. The insulatingfilm 116 is in contact with the source region 108 s and the drain region108 d, so that nitrogen or hydrogen that is contained in the insulatingfilm 116 is added to the source region 108 s and the drain region 108 d.The source region 108 s and the drain region 108 d each have a highcarrier density when nitrogen or hydrogen is added thereto.

The transistor 100A may further include an insulating film 118 over theinsulating film 116, a conductive film 120 a electrically connected tothe source region 108 s through an opening 141 a provided in theinsulating films 116 and 118, and a conductive film 120 b electricallyconnected to the drain region 108 d through an opening 141 b provided inthe insulating films 116 and 118. In addition, an insulating film 122may be provided over the insulating film 118, the conductive film 120 a,and the conductive film 120 b. Although the structure where theinsulating film 122 is provided is shown in FIGS. 21B and 21C, oneembodiment of the present invention is not limited thereto, and theinsulating film 122 is not necessarily provided.

In this specification and the like, the insulating film 104 may bereferred to as a first insulating film, the insulating film 110 may bereferred to as a second insulating film, the insulating film 116 may bereferred to as a third insulating film, the insulating film 118 may bereferred to as a fourth insulating film, and the insulating film 122 maybe referred to as a fifth insulating film. The insulating film 104functions as a first gate insulating film and the insulating film 110functions as a second gate insulating film. The insulating films 116 and118 function as a protective insulating film and the insulating film 122functions as a planarization film.

The insulating film 110 includes an excess oxygen region. Since theinsulating film 110 includes the excess oxygen region, excess oxygen canbe supplied to the channel region 108 i included in the oxidesemiconductor film 108. As a result, oxygen vacancies that might beformed in the channel region 108 i can be filled with excess oxygen,which can provide a highly reliable semiconductor device.

To supply excess oxygen to the oxide semiconductor film 108, excessoxygen may be supplied to the insulating film 104 that is formed underthe oxide semiconductor film 108. In that case, excess oxygen containedin the insulating film 104 might also be supplied to the source region108 s and the drain region 108 d included in the oxide semiconductorfilm 108. When excess oxygen is supplied to the source region 108 s andthe drain region 108 d, the resistance of the source region 108 s andthe drain region 108 d might be increased.

In contrast, in the structure in which the insulating film 110 formedover the oxide semiconductor film 108 contains excess oxygen, excessoxygen can be selectively supplied only to the channel region 108 i.Alternatively, the carrier density of the source and drain regions 108 sand 108 d can be selectively increased after excess oxygen is suppliedto the channel region 108 i and the source and drain regions 108 s and108 d, in which case an increase in the resistance of the source anddrain regions 108 s and 108 d can be prevented.

Furthermore, each of the source region 108 s and the drain region 108 dincluded in the oxide semiconductor film 108 preferably contains anelement that forms an oxygen vacancy or an element that is bonded to anoxygen vacancy. Typical examples of the element that forms an oxygenvacancy or the element that is bonded to an oxygen vacancy includehydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur,chlorine, titanium, and a rare gas. Typical examples of the rare gaselement include helium, neon, argon, krypton, and xenon. In the casewhere one or more of the elements that form an oxygen vacancy arecontained in the insulating film 116, the element that forms an oxygenvacancy is diffused from the insulating film 116 to the source region108 s and the drain region 108 d. In addition or alternatively, theelement that forms an oxygen vacancy is added to the source region 108 sand the drain region 108 d by impurity addition treatment.

An impurity element added to the oxide semiconductor film cuts a bondbetween a metal element and oxygen in the oxide semiconductor film, sothat an oxygen vacancy is formed. Alternatively, when an impurityelement is added to the oxide semiconductor film, oxygen bonded to ametal element in the oxide semiconductor film is bonded to the impurityelement and detached from the metal element, so that an oxygen vacancyis formed. As a result, the oxide semiconductor film has a highercarrier density, and thus, the conductivity thereof becomes higher.

FIG. 22 is an enlarged view showing the oxide semiconductor film 108 inFIG. 21B and its vicinity. As illustrated in FIG. 22, oxygen (O)released from the insulating film 110 because of heat treatment or thelike is supplied to the channel region 108 i, so that oxygen vacanciesare reduced. As a result, the channel region 108 i can be of an i-type.Meanwhile, hydrogen (H) is supplied to the source region 108 s and thedrain region 108 d and this hydrogen and an oxygen vacancy are bonded.Thus, the source region 108 s and the drain region 108 d can be of ann-type. Examples of the above hydrogen include hydrogen contained in adeposition gas used for forming the insulating film 116 and hydrogenreleased from the insulating film 116 because of heat treatment or thelike.

The conductive film 106 illustrated in FIGS. 21B and 21C functions as afirst gate electrode and the conductive film 112 functions as a secondgate electrode. The conductive film 120 a functions as a sourceelectrode and the conductive film 120 b functions as a drain electrode.

As illustrated in FIG. 21C, an opening 143 is provided in the insulatingfilms 104 and 110. The conductive film 106 is electrically connected tothe conductive film 112 through the opening 143. Thus, the samepotential is applied to the conductive film 106 and the conductive film112. Note that different potentials may be applied to the conductivefilm 106 and the conductive film 112 without providing the opening 143.Alternatively, the conductive film 106 may be used as a light-shieldingfilm without providing the opening 143. For example, when the conductivefilm 106 is formed using a light-shielding material, light irradiationof the channel region 108 i from the bottom can be reduced.

As illustrated in FIGS. 21B and 21C, the oxide semiconductor film 108faces the conductive film 106 functioning as the first gate electrodeand the conductive film 112 functioning as the second gate electrode andis positioned between the two conductive films functioning as the gateelectrodes.

Furthermore, the length of the conductive film 112 in the channel widthdirection is larger than the length of the oxide semiconductor film 108in the channel width direction. In the channel width direction, thewhole oxide semiconductor film 108 is covered with the conductive film112 with the insulating film 110 placed therebetween. Since theconductive film 112 is connected to the conductive film 106 through theopening 143 provided in the insulating films 104 and 110, a side surfaceof the oxide semiconductor film 108 in the channel width direction facesthe conductive film 112 with the insulating film 110 placedtherebetween.

In other words, in the channel width direction of the transistor 100A,the conductive films 106 and 112 are connected to each other through theopening 143 provided in the insulating films 104 and 110, and theconductive films 106 and 112 surround the oxide semiconductor film 108with the insulating films 104 and 110 positioned therebetween.

Such a structure enables the oxide semiconductor film 108 included inthe transistor 100A to be electrically surrounded by electric fields ofthe conductive film 106 functioning as the first gate electrode and theconductive film 112 functioning as the second gate electrode. A devicestructure of a transistor, like that of the transistor 100A, in whichelectric fields of a first gate electrode and a second gate electrodeelectrically surround the oxide semiconductor film 108 in which achannel region is formed can be referred to as a surrounded channel(S-channel) structure. Note that the transistor 100A can also bereferred to as a dual-gate transistor from the number of its gateelectrodes.

Since the transistor 100A has the S-channel structure, an electric fieldfor inducing a channel can be effectively applied to the oxidesemiconductor film 108 by the conductive film 106 or the conductive film112; thus, the current drive capability of the transistor 100A can beimproved and high on-state current characteristics can be obtained.Owing to the high on-state current, it is possible to reduce the size ofthe transistor 100A. Furthermore, since the transistor 100A has astructure in which the oxide semiconductor film 108 is surrounded by theconductive film 106 and the conductive film 112, the mechanical strengthof the transistor 100A can be increased.

When seen in the channel width direction of the transistor 100A, anopening different from the opening 143 may be formed on the side of theoxide semiconductor film 108 on which the opening 143 is not formed.

The transistor 100A may be called a top-gate self-aligned (TGSA) FETfrom the position of the conductive film 112 relative to the oxidesemiconductor film 108 or the formation method of the conductive film112. Note that the semiconductor device of one embodiment of the presentinvention is not limited to the above example and may be a bottom-gatetop-contact (BGTC) FET.

<2-2. Components of Transistor>

Next, details of the components of the transistor in FIGS. 21A to 21Cwill be described.

[Substrate]

The substrate 102 can be formed using a material having heat resistancehigh enough to withstand heat treatment in the manufacturing process.

Specifically, non-alkali glass, soda-lime glass, alkali glass, crystalglass, quartz, sapphire, or the like can be used. Alternatively, aninorganic insulating film may be used. Examples of the inorganicinsulating film include a silicon oxide film, a silicon nitride film, asilicon oxynitride film, and an aluminum oxide film.

The non-alkali glass may have a thickness of greater than or equal to0.2 mm and less than or equal to 0.7 mm, for example. The non-alkaliglass may be polished to obtain the above thickness.

As the non-alkali glass, a large-area glass substrate having any of thefollowing sizes can be used: the 6th generation (1500 mm×1850 mm), the7th generation (1870 mm×2200 mm), the 8th generation (2200 mm×2400 mm),the 9th generation (2400 mm×2800 mm), and the 10th generation (2950mm×3400 mm). Thus, a large-sized display device can be manufactured.

Alternatively, as the substrate 102, a single-crystal semiconductorsubstrate or a polycrystalline semiconductor substrate made of siliconor silicon carbide, a compound semiconductor substrate made of silicongermanium or the like, an SOI substrate, or the like may be used.

For the substrate 102, an inorganic material such as a metal may beused. Examples of the inorganic material such as a metal includestainless steel and aluminum.

Alternatively, for the substrate 102, an organic material such as aresin, a resin film, or plastic may be used. Examples of the resin filminclude polyester, polyolefin, polyamide (e.g., nylon or aramid),polyimide, polycarbonate, polyurethane, an acrylic resin, an epoxyresin, polyethylene terephthalate (PET), polyethylene naphthalate (PEN),polyether sulfone (PES), and a resin having a siloxane bond.

For the substrate 102, a composite material of an inorganic material andan organic material may be used. Examples of the composite materialinclude a resin film to which a metal plate or a thin glass plate isbonded, a resin film into which a fibrous or particulate metal or afibrous or particulate glass is dispersed, and an inorganic materialinto which a fibrous or particulate resin is dispersed.

The substrate 102 can at least support films or layers formed thereoveror thereunder and may be one or more of an insulating film, asemiconductor film, and a conductive film.

[First Insulating Film]

The insulating film 104 can be formed by a sputtering method, a CVDmethod, an evaporation method, a pulsed laser deposition (PLD) method, aprinting method, a coating method, or the like as appropriate. Forexample, the insulating film 104 can be formed to have a single-layerstructure or a stacked-layer structure of an oxide insulating filmand/or a nitride insulating film. To improve the properties of theinterface with the oxide semiconductor film 108, at least a region ofthe insulating film 104 which is in contact with the oxide semiconductorfilm 108 is preferably formed using an oxide insulating film. When theinsulating film 104 is formed using an oxide insulating film from whichoxygen is released by heating, oxygen contained in the insulating film104 can be moved to the oxide semiconductor film 108 by heat treatment.

The thickness of the insulating film 104 can be greater than or equal to50 nm, greater than or equal to 100 nm and less than or equal to 3000nm, or greater than or equal to 200 nm and less than or equal to 1000nm. By increasing the thickness of the insulating film 104, the amountof oxygen released from the insulating film 104 can be increased, andinterface states at the interface between the insulating film 104 andthe oxide semiconductor film 108 and oxygen vacancies included in thechannel region 108 i of the oxide semiconductor film 108 can be reduced.

For example, the insulating film 104 can be formed to have asingle-layer structure or stacked-layer structure of a silicon oxidefilm, a silicon oxynitride film, a silicon nitride oxide film, a siliconnitride film, an aluminum oxide film, a hafnium oxide film, a galliumoxide film, a Ga—Zn oxide film, or the like. In this embodiment, theinsulating film 104 has a stacked-layer structure of a silicon nitridefilm and a silicon oxynitride film. With the insulating film 104 havingsuch a layered structure including a silicon nitride film as a lowerlayer and a silicon oxynitride film as an upper layer, oxygen can beefficiently introduced into the oxide semiconductor film 108.

[Oxide Semiconductor Film]

It is favorable that the above-described composite oxide semiconductoror C/IGZO is used for the oxide semiconductor film 108.

[Second Insulating Film]

The insulating film 110 has a function of supplying oxygen to the oxidesemiconductor film 108, particularly to the channel region 108 i. Theinsulating film 110 can be formed to have a single-layer structure or astacked-layer structure of an oxide insulating film and/or a nitrideinsulating film, for example. To improve the interface properties withthe oxide semiconductor film 108, a region which is in the insulatingfilm 110 and in contact with the oxide semiconductor film 108 ispreferably formed using at least an oxide insulating film. For example,a silicon oxide film, a silicon oxynitride film, a silicon nitride oxidefilm, or a silicon nitride film can be used as the insulating film 110.

The thickness of the insulating film 110 can be greater than or equal to5 nm and less than or equal to 400 nm, greater than or equal to 5 nm andless than or equal to 300 nm, or greater than or equal to 10 nm and lessthan or equal to 250 nm.

It is preferable that the insulating film 110 have few defects andtypically have as few signals observed by electron spin resonance (ESR)spectroscopy as possible. Examples of the signals include a signal dueto an E′ center observed at a g-factor of 2.001. Note that the E′ centeris due to the dangling bond of silicon. As the insulating film 110, asilicon oxide film or a silicon oxynitride film whose spin density of asignal due to the E′ center is lower than or equal to 3×10¹⁷ spins/cm³,preferably lower than or equal to 5×10¹⁶ spins/cm³ may be used.

In addition to the above-described signal, a signal due to nitrogendioxide (NO₂) might be observed in the insulating film 110. The signalis divided into three signals according to the N nuclear spin; a firstsignal, a second signal, and a third signal. The first signal isobserved at a g-factor of greater than or equal to 2.037 and less thanor equal to 2.039. The second signal is observed at a g-factor ofgreater than or equal to 2.001 and less than or equal to 2.003. Thethird signal is observed at a g-factor of greater than or equal to 1.964and less than or equal to 1.966.

It is suitable to use an insulating film whose spin density of a signaldue to nitrogen dioxide (NO₂) is higher than or equal to 1×10¹⁷spins/cm³ and lower than 1×10¹⁸ spins/cm³ as the insulating film 110,for example.

Note that nitrogen oxide (NO_(x)) such as nitrogen dioxide (NO₂) forms astate in the insulating film 110. The state is positioned in the energygap of the oxide semiconductor film 108. Thus, when nitrogen oxide(NO_(x)) is diffused to the interface between the insulating film 110and the oxide semiconductor film 108, an electron might be trapped bythe state on the insulating film 110 side. As a result, the trappedelectron remains in the vicinity of the interface between the insulatingfilm 110 and the oxide semiconductor film 108, leading to a positiveshift of the threshold voltage of the transistor. Accordingly, the useof a film with a low nitrogen oxide content as the insulating film 110can reduce a shift of the threshold voltage of the transistor.

As an insulating film that releases a small amount of nitrogen oxide(NO_(x)), for example, a silicon oxynitride film can be used. Thesilicon oxynitride film releases more ammonia than nitrogen oxide(NO_(x)) in thermal desorption spectroscopy (TDS); the typical releasedamount of ammonia is greater than or equal to 1×10¹⁸/cm³ and less thanor equal to 5×10¹⁹/cm³. Note that the released amount of ammonia is thetotal amount of ammonia released by heat treatment in a range of 50° C.to 650° C. or 50° C. to 550° C. in TDS.

Since nitrogen oxide (NO_(x)) reacts with ammonia and oxygen in heattreatment, the use of an insulating film that releases a large amount ofammonia reduces nitrogen oxide (NO_(x)).

Note that in the case where the insulating film 110 is analyzed by SIMS,nitrogen concentration in the film is preferably lower than or equal to6×10²⁰ atoms/cm³.

The insulating film 110 may be formed using a high-k material such ashafnium silicate (HfSiO_(x)), hafnium silicate containing nitrogen(HfSi_(x)O_(y)N_(z)), hafnium aluminate containing nitrogen(HfAl_(x)O_(y)N_(z)), or hafnium oxide. The use of such a high-kmaterial enables a reduction in gate leakage current of a transistor.

[Third Insulating Film]

The insulating film 116 contains nitrogen or hydrogen. The insulatingfilm 116 may contain fluorine. As the insulating film 116, for example,a nitride insulating film can be used. The nitride insulating film canbe formed using silicon nitride, silicon nitride oxide, siliconoxynitride, silicon nitride fluoride, silicon fluoronitride, or thelike. The hydrogen concentration in the insulating film 116 ispreferably higher than or equal to 1×10²² atoms/cm³. Furthermore, theinsulating film 116 is in contact with the source region 108 s and thedrain region 108 d of the oxide semiconductor film 108. Thus, theconcentration of an impurity (nitrogen or hydrogen) in the source region108 s and the drain region 108 d in contact with the insulating film 116is increased, leading to an increase in the carrier density of thesource region 108 s and the drain region 108 d.

[Fourth Insulating Film]

As the insulating film 118, an oxide insulating film can be used.Alternatively, a layered film of an oxide insulating film and a nitrideinsulating film can be used as the insulating film 118. The insulatingfilm 118 can be formed using, for example, silicon oxide, siliconoxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide,gallium oxide, or a Ga—Zn oxide.

Furthermore, the insulating film 118 preferably functions as a barrierfilm against hydrogen, water, and the like from the outside.

The thickness of the insulating film 118 can be greater than or equal to30 nm and less than or equal to 500 nm, or greater than or equal to 100nm and less than or equal to 400 nm.

[Fifth Insulating Film]

The insulating film 122 has an insulating property and is formed usingan inorganic material or an organic material. Examples of the inorganicmaterial include silicon oxide, silicon oxynitride, silicon nitrideoxide, silicon nitride, aluminum oxide, and aluminum nitride. Examplesof the organic material include photosensitive resin materials such asan acrylic resin and a polyimide resin.

[Conductive Film]

The conductive films 106, 112, 120 a, and 120 b can be formed by asputtering method, a vacuum evaporation method, a pulsed laserdeposition (PLD) method, a thermal CVD method, or the like. As each ofthe conductive films 106, 112, 120 a, and 120 b, a metal film havingconductivity, a conductive film having a function of reflecting visiblelight, or a conductive film having a function of transmitting visiblelight may be used.

A material containing a metal element selected from aluminum, gold,platinum, silver, copper, chromium, tantalum, titanium, molybdenum,tungsten, nickel, iron, cobalt, palladium, and manganese can be used forthe metal film having conductivity. Alternatively, an alloy containingany of the above metal elements may be used.

For the metal film having conductivity, specifically a two-layerstructure in which a copper film is stacked over a titanium film, atwo-layer structure in which a copper film is stacked over a titaniumnitride film, a two-layer structure in which a copper film is stackedover a tantalum nitride film, a three-layer structure in which atitanium film, a copper film, and a titanium film are stacked in thisorder, or the like may be used. In particular, a conductive filmcontaining a copper element is preferably used because the resistancecan be reduced. As an example of the conductive film containing a copperelement, an alloy film containing copper and manganese is given. Thealloy film is favorable because it can be processed by a wet etchingmethod.

Note that a tantalum nitride film is preferably used for the conductivefilms 106, 112, 120 a, and 120 b. A tantalum nitride film hasconductivity and a high barrier property against copper or hydrogen.Because a tantalum nitride film releases little hydrogen from itself, itcan be favorably used as a metal film in contact with the oxidesemiconductor film 108 or a metal film in the vicinity of the oxidesemiconductor film 108.

As the metal film having conductivity, a conductive macromolecule or aconductive polymer may be used.

For the conductive film having a function of reflecting visible light, amaterial containing a metal element selected from gold, silver, copper,and palladium can be used. In particular, a conductive film containing asilver element is preferably used because reflectance of visible lightcan be improved.

For the conductive film having a function of transmitting visible light,a material containing an element selected from indium, tin, zinc,gallium, and silicon can be used. Specifically, an In oxide, a Zn oxide,an In—Sn oxide (also referred to as ITO), an In—Sn—Si oxide (alsoreferred to as ITSO), an In—Zn oxide, an In—Ga—Zn oxide, or the like canbe used.

As the conductive film having a function of transmitting visible light,a film containing graphene or graphite may be used. The film containinggraphene can be formed in the following manner: a film containinggraphene oxide is formed and is reduced. As a reducing method, a methodwith application of heat, a method using a reducing agent, or the likecan be employed.

The conductive films 112, 120 a, and 120 b can be formed by electrolessplating. As a material that can be deposited by electroless plating, forexample, one or more elements selected from Cu, Ni, Al, Au, Sn, Co, Ag,and Pd can be used. It is further favorable to use Cu or Ag because theresistance of the conductive film can be reduced.

When the conductive film is formed by electroless plating, a diffusionprevention film may be formed under the conductive film to preventcomponent elements of the conductive film from diffusing outward. A seedlayer that can make the conductive film grow may be formed between thediffusion prevention film and the conductive film. The diffusionprevention film can be formed by sputtering, for example. For thediffusion prevention film, a tantalum nitride film or a titanium nitridefilm can be used, for example. The seed layer can be formed byelectroless plating. For the seed layer, a material similar to thematerial for the conductive film that can be formed by electrolessplating can be used.

Note that an oxide semiconductor typified by an In—Ga—Zn oxide may beused for the conductive film 112. The oxide semiconductor can have ahigh carrier density when nitrogen or hydrogen is supplied from theinsulating film 116. In other words, the oxide semiconductor functionsas an oxide conductor (OC). Accordingly, the oxide semiconductor can beused for a gate electrode.

The conductive film 112 can have, for example, a single-layer structureof an oxide conductor (OC), a single-layer structure of a metal film, ora stacked-layer structure of an oxide conductor (OC) and a metal film.

Note that it is favorable that the conductive film 112 has asingle-layer structure of a light-shielding metal film or astacked-layer structure of an oxide conductor (OC) and a light-shieldingmetal film because the channel region 108 i formed under the conductivefilm 112 can be shielded from light. In the case where the conductivefilm 112 has a stacked-layer structure of an oxide semiconductor or anoxide conductor (OC) and a light-shielding metal film, formation of ametal film (e.g., a titanium film or a tungsten film) over the oxidesemiconductor or the oxide conductor (OC) produces any of the followingeffects: the resistance of the oxide semiconductor or the oxideconductor (OC) is reduced by the diffusion of the constituent element ofthe metal film to the oxide semiconductor or oxide conductor (OC) side,the resistance is reduced by damage (e.g., sputtering damage) during thedeposition of the metal film, and the resistance is reduced when oxygenvacancies are formed by the diffusion of oxygen in the oxidesemiconductor or the oxide conductor (OC) to the metal film.

The thickness of the conductive films 106, 112, 120 a, and 120 b can begreater than or equal to 30 nm and less than or equal to 500 nm, orgreater than or equal to 100 nm and less than or equal to 400 nm.

2-3. Structure Example 2 of Transistor

FIGS. 23A and 23B are cross-sectional views of a transistor 100B. FIGS.24A and 24B are cross-sectional views of a transistor 100C. FIGS. 25Aand 25B are cross-sectional views of a transistor 100D. The top views ofthe transistors 100B, 100C, and 100D are not illustrated because theyare similar to the top view of the transistor 100A in FIG. 21A.

The transistor 100B illustrated in FIGS. 23A and 23B is different fromthe transistor 100A in the layered structure of the conductive film 112,the shape of the conductive film 112, and the shape of the insulatingfilm 110.

The conductive film 112 in the transistor 100B includes a conductivefilm 112_1 over the insulating film 110 and the conductive film 112_2over the conductive film 112_1. For example, an oxide conductive film isused as the conductive film 112_1, so that excess oxygen can be added tothe insulating film 110. The oxide conductive film can be formed by asputtering method in an atmosphere containing an oxygen gas. As theoxide conductive film, an oxide film containing indium and tin, an oxidefilm containing tungsten and indium, an oxide film containing tungsten,indium, and zinc, an oxide film containing titanium and indium, an oxidefilm containing titanium, indium, and tin, an oxide film containingindium and zinc, an oxide film containing silicon, indium, and tin, oran oxide film containing indium, gallium, and zinc can be used, forexample.

As illustrated in FIG. 23B, the conductive film 112_2 is connected tothe conductive film 106 through the opening 143. By forming the opening143 after a conductive film to be the conductive film 112_1 is formed,the shape illustrated in FIG. 23B can be obtained. In the case where anoxide conductive film is used as the conductive film 112_1, thestructure in which the conductive film 112_2 is connected to theconductive film 106 can decrease the contact resistance between theconductive film 112 and the conductive film 106.

The conductive film 112 and the insulating film 110 in the transistor100B have a tapered shape. More specifically, the lower end portion ofthe conductive film 112 is located outward from the upper end portion ofthe conductive film 112. The lower end portion of the insulating film110 is located outward from the upper end portion of the insulating film110. In addition, the lower end portion of the conductive film 112 isformed in substantially the same position as that of the upper endportion of the insulating film 110.

It is favorable that the conductive film 112 and the insulating film 110of the transistor 100B are formed to have tapered shapes because thecoverage with the insulating film 116 can be high as compared with thecase of the transistor 100A in which the conductive film 112 and theinsulating film 110 have rectangular shapes.

The other components of the transistor 100B are similar to those of thetransistor 100A described above and have similar effects.

The transistor 100C illustrated in FIGS. 24A and 24B is different fromthe transistor 100A in the layered structure of the conductive film 112,the shape of the conductive film 112, and the shape of the insulatingfilm 110.

The conductive film 112 in the transistor 100C includes the conductivefilm 112_1 over the insulating film 110 and the conductive film 112_2over the conductive film 112_1. A lower end portion of the conductivefilm 112_1 is located outward from an upper end portion of theconductive film 112_2. For example, the conductive film 112_1, theconductive film 112_2, and the insulating film 110 are processed withone mask, the conductive film 112_2 is processed by a wet etchingmethod, and the conductive film 112_1 and the insulating film 110 areprocessed by a dry etching method, whereby the above-described structurecan be obtained.

With the structure of the transistor 100C, regions 108 f are formed inthe oxide semiconductor film 108 in some cases. The regions 108 f areformed between the channel region 108 i and the source region 108 s andbetween the channel region 108 i and the drain region 108 d.

The regions 108 f function as high-resistance regions or low-resistanceregions. The high-resistance regions have the same level of resistanceas the channel region 108 i and do not overlap with the conductive film112 functioning as a gate electrode. In the case where the regions 108 fare high-resistance regions, the regions 108 f function as offsetregions. To suppress a decrease in the on-state current of thetransistor 100C, the regions 108 f functioning as offset regions mayeach have a length of 1 μm or less in the channel length (L) direction.

The low-resistance regions have a resistance that is lower than that ofthe channel region 108 i and higher than that of the source region 108 sand the drain region 108 d. In the case where the regions 108 f arelow-resistance regions, the regions 108 f function as lightly dopeddrain (LDD) regions. The regions 108 f functioning as LDD regions canrelieve an electric field in the drain region, thereby reducing a changein the threshold voltage of the transistor due to the electric field inthe drain region.

Note that in the case where the regions 108 f serve as LDD regions, forexample, the regions 108 f are formed by supplying one or more ofnitrogen, hydrogen, and fluorine from the insulating film 116 to theregions 108 f or by adding an impurity element from above the conductivefilm 112_1 using the insulating film 110 and the conductive film 112_1as a mask so that the impurity element is added to the oxidesemiconductor film 108 through the conductive film 112_1 and theinsulating film 110.

As illustrated in FIG. 24B, the conductive film 112_2 is connected tothe conductive film 106 through the opening 143.

The other components of the transistor 100C are similar to those of thetransistor 100A described above and have similar effects.

The transistor 100D illustrated in FIGS. 25A and 25B is different fromthe transistor 100A in the layered structure of the conductive film 112,the shape of the conductive film 112, and the shape of the insulatingfilm 110.

The conductive film 112 in the transistor 100D includes the conductivefilm 112_1 over the insulating film 110 and the conductive film 112_2over the conductive film 112_1. A lower end portion of the conductivefilm 112_1 is located outward from a lower end portion of the conductivefilm 112_2. Furthermore, a lower end portion of the insulating film 110is located outward from the lower end portion of the conductive film112_1. For example, the conductive film 112_1, the conductive film112_2, and the insulating film 110 are processed with one mask, theconductive film 112_2 and the conductive film 112_1 are processed by awet etching method, and the insulating film 110 is processed by a dryetching method, whereby the above-described structure can be obtained.

As in the transistor 100C, the regions 108 f are formed in the oxidesemiconductor film 108 in the transistor 100D, in some cases. Theregions 108 f are formed between the channel region 108 i and the sourceregion 108 s and between the channel region 108 i and the drain region108 d.

As illustrated in FIG. 25B, the conductive film 112_2 is connected tothe conductive film 106 through the opening 143.

The other components of the transistor 100D are similar to those of thetransistor 100A described above and have similar effects.

2-4. Structure Example 3 of Transistor

FIGS. 26A and 26B are cross-sectional views of a transistor 100E. FIGS.27A and 27B are cross-sectional views of a transistor 100F. FIGS. 28Aand 28B are cross-sectional views of a transistor 100G. FIGS. 29A and29B are cross-sectional views of a transistor 100H. FIGS. 30A and 30Bare cross-sectional views of a transistor 100J. The top views of thetransistors 100E, 100F, 100G, 100H, and 100J are not illustrated becausethey are similar to the top view of the transistor 100A in FIG. 21A.

The transistors 100E, 100F, 100G, 100H, and 100J are different from theabove-described the transistor 100A in the structure of the oxidesemiconductor film 108. The other components are similar to those of thetransistor 100A and have similar effects.

The oxide semiconductor film 108 of the transistor 100E illustrated inFIGS. 26A and 26B includes an oxide semiconductor film 108_1 over theinsulating film 104, an oxide semiconductor film 108_2 over the oxidesemiconductor film 108_1, and an oxide semiconductor film 108_3 over theoxide semiconductor film 108_2. The channel region 108 i, the sourceregion 108 s, and the drain region 108 d each have a three-layerstructure of the oxide semiconductor film 108_1, the oxide semiconductorfilm 108_2, and the oxide semiconductor film 108_3.

The oxide semiconductor film 108 of the transistor 100F illustrated inFIGS. 27A and 27B includes the oxide semiconductor film 108_2 over theinsulating film 104, and the oxide semiconductor film 108_3 over theoxide semiconductor film 108_2. The channel region 108 i, the sourceregion 108 s, and the drain region 108 d each have a two-layer structureof the oxide semiconductor film 108_2 and the oxide semiconductor film108_3.

The oxide semiconductor film 108 of the transistor 100G illustrated inFIGS. 28A and 28B includes the oxide semiconductor film 108_1 over theinsulating film 104, and the oxide semiconductor film 108_2 over theoxide semiconductor film 108_1. The channel region 108 i, the sourceregion 108 s, and the drain region 108 d each have a two-layer structureof the oxide semiconductor film 108_1 and the oxide semiconductor film108_2.

The oxide semiconductor film 108 of the transistor 100H illustrated inFIGS. 29A and 29B includes the oxide semiconductor film 108_1 over theinsulating film 104, the oxide semiconductor film 108_2 over the oxidesemiconductor film 108_1, and the oxide semiconductor film 108_3 overthe oxide semiconductor film 108_2. The channel region 108 i has athree-layer structure of the oxide semiconductor film 108_1, the oxidesemiconductor film 108_2, and the oxide semiconductor film 108_3. Thesource region 108 s and the drain region 108 d each have a two-layerstructure of the oxide semiconductor film 108_1 and the oxidesemiconductor film 108_2. Note that in the cross section of thetransistor 100H in the channel width (W) direction, the oxidesemiconductor film 108_3 covers side surfaces of the oxide semiconductorfilm 108_1 and the oxide semiconductor film 108_2.

The oxide semiconductor film 108 of the transistor 100J illustrated inFIGS. 30A and 30B includes the oxide semiconductor film 108_2 over theinsulating film 104, and the oxide semiconductor film 108_3 over theoxide semiconductor film 108_2. The channel region 108 i has a two-layerstructure of the oxide semiconductor film 108_2 and the oxidesemiconductor film 108_3. The source region 108 s and the drain region108 d each have a single-layer structure of the oxide semiconductor film108_2. Note that in the cross section of the transistor 100J in thechannel width (W) direction, the oxide semiconductor film 108_3 coversside surfaces of the oxide semiconductor film 108_2.

A side surface of the channel region 108 i in the channel width (W)direction or a region in the vicinity of the side surface is easilydamaged by processing, resulting in a defect (e.g., oxygen vacancy), oreasily contaminated by an impurity attached thereto. Therefore, evenwhen the channel region 108 i is substantially intrinsic, stress such asan electric field applied thereto activates the side surface of thechannel region 108 i in the channel width (W) direction or the region inthe vicinity of the side surface and turns it into a low-resistance(n-type) region easily. Moreover, if the side surface of the channelregion 108 i in the channel width (W) direction or the region in thevicinity of the side surface is an n-type region, a parasitic channelmay be formed because the n-type region serves as a carrier path.

Thus, in the transistor 100H and the transistor 100J, the channel region108 i has a stacked-layer structure and side surfaces of the channelregion 108 i in the channel width (W) direction are covered with onelayer of the stacked layers. With such a structure, defects on or in thevicinity of the side surfaces of the channel region 108 i can besuppressed or adhesion of an impurity to the side surfaces of thechannel region 108 i or to regions in the vicinity of the side surfacescan be reduced.

[Band Structure]

Here, a band structure of the insulating film 104, the oxidesemiconductor films 108_1, 1082, and 108_3, and the insulating film 110,a band structure of the insulating film 104, the oxide semiconductorfilms 108_2 and 108_3, and the insulating film 110, and a band structureof the insulating film 104, the oxide semiconductor films 108_1 and1082, and the insulating film 110 will be described with reference toFIGS. 31A to 31C. Note that FIGS. 31A to 31C are each a band structureof the channel region 108_1.

FIG. 31A shows an example of a band structure in the thickness directionof a stack including the insulating film 104, the oxide semiconductorfilms 108_1, 108_2, and 108_3, and the insulating film 110. FIG. 31Bshows an example of a band structure in the thickness direction of astack including the insulating film 104, the oxide semiconductor films108_2 and 108_3, and the insulating film 110. FIG. 31C shows an exampleof a band structure in the thickness direction of a stack including theinsulating film 104, the oxide semiconductor films 108_1 and 108_2, andthe insulating film 110. For easy understanding, the band structuresshow the conduction band minimum (E_(c)) of the insulating film 104, theoxide semiconductor films 108_1, 108_2, and 108_3, and the insulatingfilm 110.

In the band structure of FIG. 31A, a silicon oxide film is used as eachof the insulating films 104 and 110, an oxide semiconductor film formedusing a metal oxide target whose atomic ratio of In to Ga and Zn is1:3:2 is used as the oxide semiconductor film 108_1, an oxidesemiconductor film formed using a metal oxide target whose atomic ratioof In to Ga and Zn is 4:2:4.1 is used as the oxide semiconductor film108_2, and an oxide semiconductor film formed using a metal oxide targetwhose atomic ratio of In to Ga and Zn is 1:3:2 is used as the oxidesemiconductor film 108_3.

In the band structure of FIG. 31B, a silicon oxide film is used as eachof the insulating films 104 and 110, an oxide semiconductor film formedusing a metal oxide target whose atomic ratio of In to Ga and Zn is4:2:4.1 is used as the oxide semiconductor film 108_2, and an oxidesemiconductor film formed using a metal oxide target whose atomic ratioof In to Ga and Zn is 1:3:2 is used as the oxide semiconductor film108_3.

In the band structure of FIG. 31C, a silicon oxide film is used as eachof the insulating films 104 and 110, an oxide semiconductor film formedusing a metal oxide target whose atomic ratio of In to Ga and Zn is1:3:2 is used as the oxide semiconductor film 108_1, and an oxidesemiconductor film formed using a metal oxide target whose atomic ratioof In to Ga and Zn is 4:2:4.1 is used as the oxide semiconductor film108_2.

As illustrated in FIG. 31A, the conduction band minimum gradually variesbetween the oxide semiconductor films 108_1, 108_2, and 108_3. Asillustrated in FIG. 31B, the conduction band minimum gradually variesbetween the oxide semiconductor films 108_2 and 108_3. As illustrated inFIG. 31C, the conduction band minimum gradually varies between the oxidesemiconductor films 108_1 and 108_2. In other words, the conduction bandminimum is continuously changed or continuously connected. To obtainsuch a band structure, there exists no impurity, which forms a defectstate such as a trap center or a recombination center, at the interfacebetween the oxide semiconductor films 108_1 and 108_2 or the interfacebetween the oxide semiconductor films 108_2 and 108_3.

To form a continuous junction between the oxide semiconductor films108_1, 108_2, and 108_3, it is necessary to form the films successivelywithout exposure to the air with a multi-chamber deposition apparatus(sputtering apparatus) provided with a load lock chamber.

With the band structure of FIG. 31A, FIG. 31B, or FIG. 31C, the oxidesemiconductor film 108_2 serves as a well, and a channel region isformed in the oxide semiconductor film 108_2 in the transistor with thestacked-layer structure.

By providing the oxide semiconductor films 108_1 and 108_3, the oxidesemiconductor film 108_2 can be distanced away from defect states.

In addition, the defect states might be more distant from the vacuumlevel than the conduction band minimum (E_(c)) of the oxidesemiconductor film 108_2 functioning as a channel region, so thatelectrons are likely to be accumulated in the defect states. When theelectrons are accumulated in the defect states, the electrons becomenegative fixed electric charge, so that the threshold voltage of thetransistor is shifted in the positive direction. Therefore, it ispreferable that the defect states be closer to the vacuum level than theconduction band minimum (E_(c)) of the oxide semiconductor film 108_2.Such a structure inhibits accumulation of electrons in the defectstates. As a result, the on-state current and the field-effect mobilityof the transistor can be increased.

The conduction band minimum of each of the oxide semiconductor films108_1 and 108_3 is closer to the vacuum level than that of the oxidesemiconductor film 108_2. A typical difference between the conductionband minimum of the oxide semiconductor film 108_2 and the conductionband minimum of each of the oxide semiconductor films 108_1 and 108_3 is0.15 eV or more or 0.5 eV or more and 2 eV or less or 1 eV or less. Thatis, the electron affinity of the oxide semiconductor film 108_2 ishigher than those of the oxide semiconductor films 108_1 and 108_3. Thedifference between the electron affinity of each of the oxidesemiconductor films 108_1 and 108_3 and the electron affinity of theoxide semiconductor film 108_2 is 0.15 eV or more or 0.5 eV or more and2 eV or less or 1 eV or less.

In such a structure, the oxide semiconductor film 108_2 serves as a mainpath of current. In other words, the oxide semiconductor film 108_2serves as a channel region, and the oxide semiconductor films 108_1 and108_3 serve as oxide insulating films. It is preferable that the oxidesemiconductor films 108_1 and 108_3 each include one or more metalelements constituting the oxide semiconductor film 108_2 in which achannel region is formed. With such a structure, interface scatteringhardly occurs at the interface between the oxide semiconductor film108_1 and the oxide semiconductor film 108_2 or at the interface betweenthe oxide semiconductor film 108_2 and the oxide semiconductor film108_3. Thus, the transistor can have high field-effect mobility becausethe movement of carriers is not hindered at the interface.

To prevent each of the oxide semiconductor films 108_1 and 108_3 fromfunctioning as part of a channel region, a material having sufficientlylow conductivity is used for the oxide semiconductor films 108_1 and108_3. Thus, the oxide semiconductor films 108_1 and 108_3 can bereferred to as oxide insulating films for such properties and/orfunctions. A material used for the oxide semiconductor films 108_1 and108_3 has a smaller electron affinity (a difference between the vacuumlevel and the conduction band minimum) than the oxide semiconductor film108_2 and is selected such that a difference (band offset) existsbetween the conduction band minimum of each of the oxide semiconductorfilms 108_1 and 108_3 and that of the oxide semiconductor film 108_2.Furthermore, to inhibit generation of a difference in threshold voltagedue to the value of the drain voltage, it is preferable to form theoxide semiconductor films 108_1 and 108_3 using a material whoseconduction band minimum is closer to the vacuum level than that of theoxide semiconductor film 108_2. For example, a difference between theconduction band minimum of the oxide semiconductor film 108_2 and theconduction band minimum of each of the oxide semiconductor films 108_1and 108_3 is preferably greater than or equal to 0.2 eV, furtherpreferably greater than or equal to 0.5 eV.

It is preferable that the oxide semiconductor films 108_1 and 108_3 nothave a spinel crystal structure. This is because if the oxidesemiconductor films 108_1 and 108_3 have a spinel crystal structure,constituent elements of the conductive films 120 a and 120 b might bediffused into the oxide semiconductor film 108_2 at the interfacebetween the spinel crystal structure and another region. Note that eachof the oxide semiconductor films 108_1 and 108_3 is preferably a CAAC-OSfilm described later, in which case a higher blocking property againstconstituent elements of the conductive films 120 a and 120 b, forexample, copper elements, can be obtained.

Although the example where an oxide semiconductor film formed using ametal oxide target whose atomic ratio of In to Ga and Zn is 1:3:2, isused as each of the oxide semiconductor films 108_1 and 108_3 isdescribed in this embodiment, one embodiment of the present invention isnot limited thereto. For example, an oxide semiconductor film formedusing a metal oxide target whose atomic ratio of In to Ga and Zn is1:1:1, 1:1:1.2, 1:3:4, 1:3:6, 1:4:5, 1:5:6, or 1:10:1 may be used aseach of the oxide semiconductor films 108_1 and 108_3. Alternatively,oxide semiconductor films formed using a metal oxide target whose atomicratio of Ga to Zn is 10:1 may be used as the oxide semiconductor films108_1 and 108_3. In that case, it is favorable that an oxidesemiconductor film formed using a metal oxide target whose atomic ratioof In to Ga and Zn is 1:1:1 is used as the oxide semiconductor film108_2 and an oxide semiconductor film formed using a metal oxide targetwhose atomic ratio of Ga to Zn is 10:1 is used as each of the oxidesemiconductor films 108_1 and 108_3 because the difference between theconduction band minimum of the oxide semiconductor film 108_2 and theconduction band minimum of the oxide semiconductor film 108_1 or 108_3can be 0.6 eV or more.

When the oxide semiconductor films 108_1 and 108_3 are formed using ametal oxide target whose atomic ratio of In to Ga and Zn is 1:1:1, theatomic ratio of In to Ga and Zn in the oxide semiconductor films 108_1and 108_3 might be 1:β1:β2 (0<⊕1≤2, 0<β2≤2). When the oxidesemiconductor films 108_1 and 108_3 are formed using a metal oxidetarget whose atomic ratio of In to Ga and Zn is 1:3:4, the atomic ratioof In to Ga and Zn in the oxide semiconductor films 108_1 and 108_3might be 1:β3:β4 (1≤β3≤5, 2≤β4≤6). When the oxide semiconductor films108_1 and 108_3 are formed using a metal oxide target whose atomic ratioof In to Ga and Zn is 1:3:6, the atomic ratio of In to Ga and Zn in theoxide semiconductor films 108_1 and 108_3 might be 1:β5:β6 (1≤β5≤5,4≤β6≤8).

2-5. Structure Example 4 of Transistor

FIG. 32A is a top view of a transistor 300A. FIG. 32B is across-sectional view taken along dashed-dotted line X1-X2 in FIG. 32A.FIG. 32C is a cross-sectional view taken along dashed-dotted line Y1-Y2in FIG. 32A. Note that in FIG. 32A, some components of the transistor300A (e.g., an insulating film functioning as a gate insulating film)are not illustrated to avoid complexity. The direction of dashed-dottedline X1-X2 may be referred to as a channel length direction, and thedirection of dashed-dotted line Y1-Y2 may be referred to as a channelwidth direction. As in FIG. 32A, some components are not illustrated insome cases in top views of transistors described below.

The transistor 300A illustrated in FIGS. 32A to 32C includes aconductive film 304 over a substrate 302, an insulating film 306 overthe substrate 302 and the conductive film 304, an insulating film 307over the insulating film 306, an oxide semiconductor film 308 over theinsulating film 307, a conductive film 312 a over the oxidesemiconductor film 308, and a conductive film 312 b over the oxidesemiconductor film 308. Over the transistor 300A, specifically, over theconductive films 312 a and 312 b and the oxide semiconductor film 308,an insulating film 314, an insulating film 316, and an insulating film318 are provided.

In the transistor 300A, the insulating films 306 and 307 function as thegate insulating films of the transistor 300A, and the insulating films314, 316, and 318 function as protective insulating films of thetransistor 300A. Furthermore, in the transistor 300A, the conductivefilm 304 functions as a gate electrode, the conductive film 312 afunctions as a source electrode, and the conductive film 312 b functionsas a drain electrode.

In this specification and the like, the insulating films 306 and 307 maybe referred to as a first insulating film, the insulating films 314 and316 may be referred to as a second insulating film, and the insulatingfilm 318 may be referred to as a third insulating film.

The transistor 300A illustrated in FIGS. 32A to 32C is a channel-etchedtransistor. The oxide semiconductor film of one embodiment of thepresent invention is suitable for a channel-etched transistor.

2-6. Structure Example 5 of Transistor

FIG. 33A is a top view of a transistor 300B. FIG. 33B is across-sectional view taken along dashed-dotted line X1-X2 in FIG. 33A.FIG. 33C is a cross-sectional view taken along dashed-dotted line Y1-Y2in FIG. 33A.

The transistor 300B illustrated in FIGS. 33A to 33C includes theconductive film 304 over the substrate 302, the insulating film 306 overthe substrate 302 and the conductive film 304, the insulating film 307over the insulating film 306, the oxide semiconductor film 308 over theinsulating film 307, the insulating film 314 over the oxidesemiconductor film 308, the insulating film 316 over the insulating film314, the conductive film 312 a electrically connected to the oxidesemiconductor film 308 through an opening 341 a provided in theinsulating films 314 and 316, and the conductive film 312 b electricallyconnected to the oxide semiconductor film 308 through an opening 341 bprovided in the insulating films 314 and 316. Over the transistor 300B,specifically, over the conductive films 312 a and 312 b and theinsulating film 316, the insulating film 318 is provided.

In the transistor 300B, the insulating films 306 and 307 each functionas a gate insulating film of the transistor 300B, the insulating films314 and 316 each function as a protective insulating film of the oxidesemiconductor film 308, and the insulating film 318 functions as aprotective insulating film of the transistor 300B. Moreover, in thetransistor 300B, the conductive film 304 functions as a gate electrode,the conductive film 312 a functions as a source electrode, and theconductive film 312 b functions as a drain electrode.

The transistor 300A illustrated in FIGS. 32A to 32C has a channel-etchedstructure, whereas the transistor 300B in FIGS. 33A to 33C has achannel-protective structure. The oxide semiconductor film of oneembodiment of the present invention is suitable for a channel-protectivetransistor as well.

2-7. Structure Example 6 of Transistor

FIG. 34A is a top view of a transistor 300C. FIG. 34B is across-sectional view taken along dashed-dotted line X1-X2 in FIG. 34A.FIG. 34C is a cross-sectional view taken along dashed-dotted line Y1-Y2in FIG. 34A.

The transistor 300C illustrated in FIGS. 34A to 34C is different fromthe transistor 300B in FIGS. 33A to 33C in the shapes of the insulatingfilms 314 and 316. Specifically, the insulating films 314 and 316 of thetransistor 300C have island shapes and are provided over a channelregion of the oxide semiconductor film 308. Other components are similarto those of the transistor 300B.

2-8. Structure Example 7 of Transistor

FIG. 35A is a top view of a transistor 300D. FIG. 35B is across-sectional view taken along dashed-dotted line X1-X2 in FIG. 35A.FIG. 35C is a cross-sectional view taken along dashed-dotted line Y1-Y2in FIG. 35A.

The transistor 300D illustrated in FIGS. 35A to 35C includes theconductive film 304 over the substrate 302, the insulating film 306 overthe substrate 302 and the conductive film 304, the insulating film 307over the insulating film 306, the oxide semiconductor film 308 over theinsulating film 307, the conductive film 312 a over the oxidesemiconductor film 308, the conductive film 312 b over the oxidesemiconductor film 308, the insulating film 314 over the oxidesemiconductor film 308 and the conductive films 312 a and 312 b, theinsulating film 316 over the insulating film 314, the insulating film318 over the insulating film 316, and conductive films 320 a and 320 bover the insulating film 318.

In the transistor 300D, the insulating films 306 and 307 function asfirst gate insulating films of the transistor 300D, and the insulatingfilms 314, 316, and 318 function as second gate insulating films of thetransistor 300D. Furthermore, in the transistor 300D, the conductivefilm 304 functions as a first gate electrode, the conductive film 320 afunctions as a second gate electrode, and the conductive film 320 bfunctions as a pixel electrode used for a display device. The conductivefilm 312 a functions as a source electrode, and the conductive film 312b functions as a drain electrode.

As illustrated in FIG. 35C, the conductive film 320 a is connected tothe conductive film 304 in an opening 342 b and an opening 342 cprovided in the insulating films 306, 307, 314, 316, and 318. Thus, thesame potential is applied to the conductive film 320 a and theconductive film 304.

The structure of the transistor 300D is not limited to that describedabove, in which the openings 342 b and 342 c are provided so that theconductive film 320 a is connected to the conductive film 304. Forexample, a structure in which only one of the openings 342 b and 342 cis provided so that the conductive film 320 a is connected to theconductive film 304, or a structure in which the conductive film 320 ais not connected to the conductive film 304 without providing theopenings 342 b and 342 c may be employed. Note that in the case wherethe conductive film 320 a is not connected to the conductive film 304,it is possible to apply different potentials to the conductive film 320a and the conductive film 304.

The conductive film 320 b is connected to the conductive film 312 bthrough an opening 342 a provided in the insulating films 314, 316, and318.

Note that the transistor 300D has the S-channel structure describedabove.

2-9. Structure Example 8 of Transistor

The oxide semiconductor film 308 included in the transistor 300A inFIGS. 32A to 32C may have a stacked-layer structure. FIGS. 36A and 36Band FIGS. 37A and 37B illustrate examples of such a case.

FIGS. 36A and 36B are cross-sectional views of a transistor 300E andFIGS. 37A and 37B are cross-sectional views of a transistor 300F. Thetop views of the transistors 300E and 300F are similar to that of thetransistor 300A illustrated in FIG. 32A.

The oxide semiconductor film 308 of the transistor 300E illustrated inFIGS. 36A and 36B includes an oxide semiconductor film 308_1, an oxidesemiconductor film 308_2, and an oxide semiconductor film 308_3. Theoxide semiconductor film 308 of the transistor 300F illustrated in FIGS.37A and 37B includes the oxide semiconductor film 308_2 and the oxidesemiconductor film 308_3.

Note that the conductive film 304, the insulating film 306, theinsulating film 307, the oxide semiconductor film 308, the oxidesemiconductor film 308_1, the oxide semiconductor film 308_2, the oxidesemiconductor film 308_3, the conductive films 312 a and 312 b, theinsulating film 314, the insulating film 316, the insulating film 318,and the conductive films 320 a and 320 b can be formed using thematerials of the conductive film 106, the insulating film 116, the oxidesemiconductor film 108, the oxide semiconductor film 108_1, the oxidesemiconductor film 108_2, the oxide semiconductor film 108_3, theconductive films 120 a and 120 b, the insulating film 104, theinsulating film 118, the insulating film 116, and the conductive film112, respectively, described above.

2-10. Structure Example 9 of Transistor

FIG. 38A is a top view of a transistor 300G. FIG. 38B is across-sectional view taken along dashed-dotted line X1-X2 in FIG. 38A.FIG. 38C is a cross-sectional view taken along dashed-dotted line Y1-Y2in FIG. 38A.

The transistor 300G illustrated in FIGS. 38A to 38C includes theconductive film 304 over the substrate 302, the insulating film 306 overthe substrate 302 and the conductive film 304, the insulating film 307over the insulating film 306, the oxide semiconductor film 308 over theinsulating film 307, the conductive film 312 a over the oxidesemiconductor film 308, the conductive film 312 b over the oxidesemiconductor film 308, the insulating film 314 over the oxidesemiconductor film 308 and the conductive films 312 a and 312 b, theinsulating film 316 over the insulating film 314, the conductive film320 a over the insulating film 316, and the conductive film 320 b overthe insulating film 316.

The insulating films 306 and 307 have an opening 351. A conductive film312 c, which is electrically connected to the conductive film 304through the opening 351, is formed over the insulating films 306 and307. The insulating films 314 and 316 have an opening 352 a that reachesthe conductive film 312 b and an opening 352 b that reaches theconductive film 312 c.

The oxide semiconductor film 308 includes the oxide semiconductor film308_2 on the conductive film 304 side and the oxide semiconductor film308_3 over the oxide semiconductor film 308_2.

The insulating film 318 is provided over the transistor 300G. Theinsulating film 318 is formed to cover the insulating film 316, theconductive film 320 a, and the conductive film 320 b.

In the transistor 300G, the insulating films 306 and 307 function asfirst gate insulating films of the transistor 300G, and the insulatingfilms 314 and 316 function as second gate insulating films of thetransistor 300G, and the insulating film 318 functions as a protectiveinsulating film of the transistor 300G. Furthermore, in the transistor300G, the conductive film 304 functions as a first gate electrode, theconductive film 320 a functions as a second gate electrode, and theconductive film 320 b functions as a pixel electrode used for a displaydevice. Moreover, in the transistor 300G, the conductive film 312 afunctions as a source electrode, the conductive film 312 b functions asa drain electrode, and the conductive film 312 c functions as aconnection electrode.

Note that the transistor 300G has the S-channel structure describedabove.

The structures of the transistors 300A to 300G can be freely combinedwith each other.

At least part of this embodiment can be implemented in combination withany of the other embodiments described in this specification asappropriate.

Embodiment 3

In this embodiment, examples of a display device that includes thesemiconductor device described in the above embodiments are describedbelow with reference to FIGS. 39 to 44, FIGS. 45A to 45D, and FIG. 46.

FIG. 39 is a top view illustrating an example of a display device. Adisplay device 700 in FIG. 39 includes a pixel portion 702 provided overa first substrate 701, a source driver circuit portion 704 and a gatedriver circuit portion 706 that are provided over the first substrate701, a sealant 712 provided to surround the pixel portion 702, thesource driver circuit portion 704, and the gate driver circuit portion706, and a second substrate 705 provided to face the first substrate701. The first substrate 701 and the second substrate 705 are sealedwith the sealant 712. That is, the pixel portion 702, the source drivercircuit portion 704, and the gate driver circuit portion 706 areenclosed by the first substrate 701, the sealant 712, and the secondsubstrate 705. Although not illustrated in FIG. 39, a display element isprovided between the first substrate 701 and the second substrate 705.

In the display device 700, a flexible printed circuit (FPC) terminalportion 708 that is electrically connected to the pixel portion 702, thesource driver circuit portion 704, and the gate driver circuit portion706 is provided in a region different from the region that is over thefirst substrate 701 and surrounded by the sealant 712. Furthermore, anFPC 716 is connected to the FPC terminal portion 708, and a variety ofsignals and the like are supplied from the FPC 716 to the pixel portion702, the source driver circuit portion 704, and the gate driver circuitportion 706. Furthermore, a signal line 710 is connected to the pixelportion 702, the source driver circuit portion 704, the gate drivercircuit portion 706, and the FPC terminal portion 708. Through thesignal line 710, a variety of signals and the like are supplied from theFPC 716 to the pixel portion 702, the source driver circuit portion 704,the gate driver circuit portion 706, and the FPC terminal portion 708.

A plurality of gate driver circuit portions 706 may be provided in thedisplay device 700. The structure of the display device 700 is notlimited to the example shown here, in which the source driver circuitportion 704 and the gate driver circuit portion 706 as well as the pixelportion 702 are formed over the first substrate 701. For example, onlythe gate driver circuit portion 706 may be formed over the firstsubstrate 701, or only the source driver circuit portion 704 may beformed over the first substrate 701. In this case, a substrate overwhich a source driver circuit, a gate driver circuit, or the like isformed (e.g., a driver circuit board formed using a single crystalsemiconductor film or a polycrystalline semiconductor film) may beformed on the first substrate 701. Note that there is no particularlimitation on the method for connecting the separately prepared drivercircuit board, and a chip on glass (COG) method, a wire bonding method,or the like can be used.

The pixel portion 702, the source driver circuit portion 704, and thegate driver circuit portion 706 included in the display device 700include a plurality of transistors.

The display device 700 can include a variety of elements. As examples ofthe elements, electroluminescent (EL) element (e.g., an EL elementcontaining organic and inorganic materials, an organic EL element, aninorganic EL element, or an LED), a light-emitting transistor element (atransistor that emits light depending on current), an electron emitter,a liquid crystal element, an electronic ink display, an electrophoreticelement, an electrowetting element, a plasma display panel (PDP), microelectro mechanical systems (MEMS) display (e.g., a grating light valve(GLV), a digital micromirror device (DMD), a digital micro shutter (DMS)element, or an interferometric modulator display (IMOD) element), apiezoelectric ceramic display, and the like can be given.

An example of a display device including an EL element is an EL display.Examples of a display device including an electron emitter include afield emission display (FED) and an SED-type flat panel display (SED:surface-conduction electron-emitter display). An example of a displaydevice including a liquid crystal element is a liquid crystal display (atransmissive liquid crystal display, a transflective liquid crystaldisplay, a reflective liquid crystal display, a direct-view liquidcrystal display, or a projection liquid crystal display). An example ofa display device including an electronic ink display or anelectrophoretic element is electronic paper. In a transflective liquidcrystal display or a reflective liquid crystal display, some or all ofpixel electrodes may function as reflective electrodes. For example,some or all of pixel electrodes may contain aluminum, silver, or thelike. In this case, a memory circuit such as an SRAM can be providedunder the reflective electrodes, leading to lower power consumption.

As a display system of the display device 700, a progressive system, aninterlace system, or the like can be employed. Furthermore, colorelements controlled in pixels at the time of color display are notlimited to three colors: R, G, and B (R, G, and B correspond to red,green, and blue, respectively). For example, four pixels of an R pixel,a G pixel, a B pixel, and a W (white) pixel may be used. Alternatively,a color element may be composed of two colors of R, G, and B as inPenTile layout. The two colors may differ depending on the colorelements. Alternatively, one or more colors of yellow, cyan, magenta,and the like may be added to RGB. Note that the size of a display regionmay differ between dots of color elements. One embodiment of thedisclosed invention is not limited to a color display device; thedisclosed invention can also be applied to a monochrome display device.

A coloring layer (also referred to as a color filter) may be used toobtain a full-color display device in which white light (W) is used fora backlight (e.g., an organic EL element, an inorganic EL element, anLED, or a fluorescent lamp). For example, a red (R) coloring layer, agreen (G) coloring layer, a blue (B) coloring layer, and a yellow (Y)coloring layer can be combined as appropriate. With the use of thecoloring layer, high color reproducibility can be obtained as comparedwith the case without the coloring layer. Here, by providing a regionwith a coloring layer and a region without a coloring layer, white lightin the region without the coloring layer may be directly utilized fordisplay. By partly providing the region without a coloring layer, adecrease in the luminance of a bright image due to the coloring layercan be suppressed, and power consumption can be reduced by approximately20% to 30% in some cases. In the case where full-color display isperformed using a self-luminous element such as an organic EL element oran inorganic EL element, elements may emit light in their respectivecolors R, G, B, Y, and W. By using a self-luminous element, powerconsumption may be further reduced as compared with the case of using acoloring layer.

As a coloring system, any of the following systems may be used: theabove-described color filter system in which part of white light isconverted into red light, green light, and blue light through colorfilters; a three-color system in which red light, green light, and bluelight are used; and a color conversion system or a quantum dot system inwhich part of blue light is converted into red light or green light.

In this embodiment, a structure including a liquid crystal element as adisplay element and a structure including an EL element as a displayelement are described with reference to FIGS. 40 to 42. FIG. 40 and FIG.41 are each a cross-sectional view taken along dashed-dotted line Q-R inFIG. 39 and illustrate the structure including a liquid crystal elementas a display element. FIG. 42 is a cross-sectional view taken alongdashed-dotted line Q-R in FIG. 39 and illustrates the structureincluding an EL element as a display element.

Portions common to FIG. 40, FIG. 41, and FIG. 42 are described first,and then, different portions are described.

3-1. Portions Common to Display Devices

The display device 700 in FIG. 40, FIG. 41, and FIG. 42 includes a leadwiring portion 711, the pixel portion 702, the source driver circuitportion 704, and the FPC terminal portion 708. The lead wiring portion711 includes the signal line 710. The pixel portion 702 includes atransistor 750 and a capacitor 790. The source driver circuit portion704 includes a transistor 752.

The transistor 750 and the transistor 752 each have a structure similarto that of the transistor 100A described above. Note that the transistor750 and the transistor 752 may each have the structure of any of theother transistors described in the above embodiments.

The transistor used in this embodiment includes an oxide semiconductorfilm that is highly purified and in which formation of oxygen vacanciesis inhibited. The transistor can have a low off-state current.Accordingly, an electrical signal such as an image signal can be heldfor a long time, and a long writing interval can be set in an on state.Accordingly, the frequency of refresh operation can be reduced, whichsuppresses power consumption.

In addition, the transistor used in this embodiment can have relativelyhigh field-effect mobility and thus is capable of high-speed operation.For example, in a liquid crystal display device that includes such atransistor capable of high-speed operation, a switching transistor in apixel portion and a driver transistor in a driver circuit portion can beformed over one substrate. That is, no additional semiconductor deviceformed using a silicon wafer or the like is needed as a driver circuit;therefore, the number of components of the semiconductor device can bereduced. In addition, by using the transistor capable of high-speedoperation in the pixel portion, a high-quality image can be provided.

The capacitor 790 includes a lower electrode and an upper electrode. Thelower electrode is formed through a step of processing a conductive filmto be a conductive film functioning as a first gate electrode of thetransistor 750. The upper electrode is formed through a step ofprocessing a conductive film to be a conductive film functioning assource and drain electrodes of the transistor 750 or a second gateelectrode of the transistor 750. Between the lower electrode and theupper electrode, an insulating film formed through a step of forming aninsulating film to be an insulating film functioning as a first gateinsulating film of the transistor 750 and insulating films formedthrough a step of forming insulating films to be insulating filmsfunctioning as protective insulating films over the transistor 750 areprovided. That is, the capacitor 790 has a stacked-layer structure inwhich an insulating film functioning as a dielectric film is positionedbetween the pair of electrodes.

In FIG. 40, FIG. 41, and FIG. 42, a planarization insulating film 770 isprovided over the transistor 750, the transistor 752, and the capacitor790.

Although FIG. 40, FIG. 41, and FIG. 42 each illustrate an example inwhich the transistor 750 included in the pixel portion 702 and thetransistor 752 included in the source driver circuit portion 704 havethe same structure, one embodiment of the present invention is notlimited thereto. For example, the pixel portion 702 and the sourcedriver circuit portion 704 may include different transistors.Specifically, a structure in which a top-gate transistor is used in thepixel portion 702 and a bottom-gate transistor is used in the sourcedriver circuit portion 704, or a structure in which a bottom-gatetransistor is used in the pixel portion 702 and a top-gate transistor isused in the source driver circuit portion 704 may be employed. Note thatthe term “source driver circuit portion 704” can be replaced by the term“gate driver circuit portion.”

The signal line 710 is formed through the same process as the conductivefilms functioning as source electrodes and drain electrodes of thetransistors 750 and 752. In the case where the signal line 710 is formedusing a material containing a copper element, signal delay or the likedue to wiring resistance is reduced, which enables display on a largescreen.

The FPC terminal portion 708 includes a connection electrode 760, ananisotropic conductive film 780, and the FPC 716. Note that theconnection electrode 760 is formed through the same process as theconductive films functioning as source electrodes and drain electrodesof the transistors 750 and 752. The connection electrode 760 iselectrically connected to a terminal included in the FPC 716 through theanisotropic conductive film 780.

For example, glass substrates can be used as the first substrate 701 andthe second substrate 705. As the first substrate 701 and the secondsubstrate 705, flexible substrates may also be used. An example of theflexible substrate is a plastic substrate.

A structure 778 is provided between the first substrate 701 and thesecond substrate 705. The structure 778 is a columnar spacer obtained byselective etching of an insulating film and is provided to control thedistance (cell gap) between the first substrate 701 and the secondsubstrate 705. Alternatively, a spherical spacer may also be used as thestructure 778.

A light-blocking film 738 functioning as a black matrix, a coloring film736 functioning as a color filter, and an insulating film 734 in contactwith the light-blocking film 738 and the coloring film 736 are providedon the second substrate 705 side.

3-2. Structure Example of Display Device Including Liquid CrystalElement

The display device 700 in FIG. 40 includes a liquid crystal element 775.The liquid crystal element 775 includes a conductive film 772, aconductive film 774, and a liquid crystal layer 776. The conductive film774 is provided on the second substrate 705 side and functions as acounter electrode. The display device 700 in FIG. 40 can display animage in such a manner that transmission or non-transmission of light iscontrolled by the alignment state in the liquid crystal layer 776 thatis changed depending on the voltage applied between the conductive film772 and the conductive film 774.

The conductive film 772 is electrically connected to the conductive filmfunctioning as the source electrode or the drain electrode of thetransistor 750. The conductive film 772 is formed over the planarizationinsulating film 770 and functions as a pixel electrode, that is, oneelectrode of the display element.

A conductive film that transmits visible light or a conductive film thatreflects visible light can be used as the conductive film 772. Forexample, a material containing an element selected from indium (In),zinc (Zn), and tin (Sn) is preferably used for the conductive film thattransmits visible light. For example, a material containing aluminum orsilver is preferably used for the conductive film that reflects visiblelight.

In the case where a conductive film that reflects visible light is usedas the conductive film 772, the display device 700 is a reflectiveliquid crystal display device. In the case where a conductive film thattransmits visible light is used as the conductive film 772, the displaydevice 700 is a transmissive liquid crystal display device.

The method for driving the liquid crystal element can be changed bychanging the structure over the conductive film 772, an example of thiscase is illustrated in FIG. 41. The display device 700 illustrated inFIG. 41 is an example of employing a horizontal electric field mode(e.g., an FFS mode) as a driving mode of the liquid crystal element. Inthe structure illustrated in FIG. 41, an insulating film 773 is providedover the conductive film 772, and the conductive film 774 is providedover the insulating film 773. In such a structure, the conductive film774 functions as a common electrode, and an electric field generatedbetween the conductive film 772 and the conductive film 774 through theinsulating film 773 can control the alignment state in the liquidcrystal layer 776.

Although not illustrated in FIG. 40 and FIG. 41, the conductive film 772and/or the conductive film 774 may be provided with an alignment film ona side in contact with the liquid crystal layer 776. Although notillustrated in FIG. 40 and FIG. 41, an optical member (opticalsubstrate) or the like, such as a polarizing member, a retardationmember, or an anti-reflection member, may be provided as appropriate.For example, circular polarization may be obtained by using a polarizingsubstrate and a retardation substrate. In addition, a backlight, asidelight, or the like may be used as a light source.

In the case where a liquid crystal element is used as the displayelement, a thermotropic liquid crystal, a low-molecular liquid crystal,a high-molecular liquid crystal, a polymer dispersed liquid crystal, aferroelectric liquid crystal, an anti-ferroelectric liquid crystal, orthe like can be used. These liquid crystal materials exhibit acholesteric phase, a smectic phase, a cubic phase, a chiral nematicphase, an isotropic phase, or the like depending on conditions.

In the case where a horizontal electric field mode is employed, a liquidcrystal exhibiting a blue phase for which an alignment film isunnecessary may be used. The blue phase is one of liquid crystal phases,which is generated just before a cholesteric phase changes into anisotropic phase when the temperature of a cholesteric liquid crystal isincreased. Since the blue phase appears only in a narrow temperaturerange, a liquid crystal composition in which several weight percent ormore of a chiral material is mixed is used for the liquid crystal layerin order to improve the temperature range. The liquid crystalcomposition containing a liquid crystal exhibiting a blue phase and achiral material has a short response time and optical isotropy, whicheliminates the need for an alignment process. An alignment film does notneed to be provided, and thus, rubbing treatment is not necessary;accordingly, electrostatic discharge damage caused by the rubbingtreatment can be prevented, and defects and damage of a liquid crystaldisplay device in the manufacturing process can be reduced. Moreover,the liquid crystal material that exhibits a blue phase has small viewingangle dependence.

In the case where a liquid crystal element is used as a display element,a twisted nematic (TN) mode, an in-plane switching (IPS) mode, a fringefield switching (FFS) mode, an axially symmetric aligned micro-cell(ASM) mode, an optical compensated birefringence (OCB) mode, aferroelectric liquid crystal (FLC) mode, an anti-ferroelectric liquidcrystal (AFLC) mode, or the like can be used.

Furthermore, a normally black liquid crystal display device such as avertical alignment (VA) mode transmissive liquid crystal display devicemay also be used. There are some examples of a vertical alignment mode;for example, a multi-domain vertical alignment (MVA) mode, a patternedvertical alignment (PVA) mode, and an ASV mode, or the like can beemployed.

<3-3. Display Device Including Light-Emitting Element>

The display device 700 illustrated in FIG. 42 includes a light-emittingelement 782. The light-emitting element 782 includes a conductive film772, an EL layer 786, and a conductive film 788. The display device 700illustrated in FIG. 42 can display an image by utilizing light emissionfrom the EL layer 786 of the light-emitting element 782. Note that theEL layer 786 contains an organic compound or an inorganic compound suchas a quantum dot.

Examples of materials that can be used for an organic compound include afluorescent material and a phosphorescent material. Examples ofmaterials that can be used for a quantum dot include a colloidal quantumdot material, an alloyed quantum dot material, a core-shell quantum dotmaterial, and a core quantum dot material. A material containingelements belonging to Groups 12 and 16, elements belonging to Groups 13and 15, or elements belonging to Groups 14 and 16, may be used.Alternatively, a quantum dot material containing an element such ascadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P),indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As), oraluminum (Al) may be used.

The above-described organic compound and the inorganic compound can bedeposited by a method such as an evaporation method (including a vacuumevaporation method), a droplet discharge method (also referred to as anink-jet method), a coating method, or a gravure printing method. A lowmolecular material, a middle molecular material (including an oligomerand a dendrimer), or a high molecular material may be included in the ELlayer 786.

Here, a method for forming the EL layer 786 by a droplet dischargemethod is described with reference to FIGS. 45A to 45D. FIGS. 45A to 45Dare cross-sectional views illustrating the method for forming the ELlayer 786.

First, the conductive film 772 is formed over the planarizationinsulating film 770, and an insulating film 730 is formed to cover partof the conductive film 772 (see FIG. 45A).

Then, a droplet 784 is discharged to an exposed portion of theconductive film 772, which is an opening of the insulating film 730,from a droplet discharge apparatus 783, so that a layer 785 containing acomposition is formed. The droplet 784 is a composition containing asolvent and is attached to the conductive film 772 (see FIG. 45B).

Note that the step of discharging the droplet 784 may be performed underreduced pressure.

Next, the solvent is removed from the layer 785 containing thecomposition, and the resulting layer is solidified to form the EL layer786 (see FIG. 45C).

The solvent may be removed by drying or heating.

Next, the conductive film 788 is formed over the EL layer 786; thus, thelight-emitting element 782 is formed (see FIG. 45D).

When the EL layer 786 is formed by a droplet discharge method asdescribed above, the composition can be selectively discharged;accordingly, waste of material can be reduced. Furthermore, alithography process or the like for shaping is not needed, and thus, theprocess can be simplified and cost reduction can be achieved.

The droplet discharge method described above is a general term for ameans including a nozzle equipped with a composition discharge openingor a means to discharge droplets such as a head having one or aplurality of nozzles.

Next, a droplet discharge apparatus used for the droplet dischargemethod is described with reference to FIG. 46. FIG. 46 is a conceptualdiagram illustrating a droplet discharge apparatus 1400.

The droplet discharge apparatus 1400 includes a droplet discharge means1403. In addition, the droplet discharge means 1403 is equipped with ahead 1405 and a head 1412.

The heads 1405 and 1412 are connected to a control means 1407, and thiscontrol means 1407 is controlled by a computer 1410; thus, apreprogrammed pattern can be drawn.

The drawing may be conducted at a timing, for example, based on a marker1411 formed over a substrate 1402. Alternatively, the reference pointmay be determined on the basis of an outer edge of the substrate 1402.Here, the marker 1411 is detected by an imaging means 1404 and convertedinto a digital signal by an image processing means 1409. Then, thedigital signal is recognized by the computer 1410, and then, a controlsignal is generated and transmitted to the control means 1407.

An image sensor or the like using a charge coupled device (CCD) or acomplementary metal-oxide-semiconductor (CMOS) can be used as theimaging means 1404. Note that information about a pattern to be formedover the substrate 1402 is stored in a storage medium 1408, and acontrol signal is transmitted to the control means 1407 based on theinformation, so that each of the heads 1405 and 1412 of the dropletdischarge means 1403 can be individually controlled. The heads 1405 and1412 are supplied with a material to be discharged from material supplysources 1413 and 1414 through pipes, respectively.

Inside the head 1405, a space as indicated by a dotted line 1406 to befilled with a liquid material and a nozzle which is a discharge outletare provided. Although it is not shown, an inside structure of the head1412 is similar to that of the head 1405. When the nozzle sizes of theheads 1405 and 1412 are different from each other, different materialswith different widths can be discharged simultaneously. Each head candischarge and draw a plurality of light emitting materials. In the caseof drawing over a large area, the same material can be simultaneouslydischarged to be drawn from a plurality of nozzles in order to improvethroughput. When a large substrate is used, the heads 1405 and 1412 canfreely scan the substrate in directions indicated by arrows X, Y, and Zin FIG. 46, and a region in which a pattern is drawn can be freely set.Thus, a plurality of the same patterns can be drawn over one substrate.

Furthermore, a step of discharging the composition may be performedunder reduced pressure. A substrate may be heated when the compositionis discharged. After discharging the composition, either drying orbaking or both of them are performed. Both the drying and baking areheat treatments but different in purpose, temperature, and time period.The steps of drying and baking are performed under normal pressure orunder reduced pressure by laser irradiation, rapid thermal annealing,heating using a heating furnace, or the like. Note that there is noparticular limitation on the timing of the heat treatment and the numberof times of the heat treatment. The temperature for performing each ofthe steps of drying and baking in a favorable manner depends on thematerials of the substrate and the properties of the composition.

In the above-described manner, the EL layer 786 can be formed with thedroplet discharge apparatus.

The display device 700 shown in FIG. 42 is described again.

In the display device 700 in FIG. 42, the insulating film 730 isprovided over the planarization insulating film 770 and the conductivefilm 772. The insulating film 730 covers part of the conductive film772. Note that the light-emitting element 782 has a top-emissionstructure. Thus, the conductive film 788 has a light-transmittingproperty and transmits light emitted from the EL layer 786. Although thetop-emission structure is described as an example in this embodiment,the structure is not limited thereto. For example, a bottom-emissionstructure in which light is emitted to the conductive film 772 side or adual-emission structure in which light is emitted to both the conductivefilm 772 side and the conductive film 788 side may also be employed.

The coloring film 736 is provided to overlap with the light-emittingelement 782, and the light-blocking film 738 is provided in the leadwiring portion 711 and the source driver circuit portion 704 to overlapwith the insulating film 730. The coloring film 736 and thelight-blocking film 738 are covered with the insulating film 734. Aspace between the light-emitting element 782 and the insulating film 734is filled with a sealing film 732. The structure of the display device700 is not limited to the example in FIG. 42, in which the coloring film736 is provided. For example, a structure without the coloring film 736may also be employed in the case where the EL layer 786 is formed byseparate coloring.

<3-4. Structure Example of Display Device Provided with Input/OutputDevice>

An input/output device may be provided in the display device 700illustrated in FIG. 41 and FIG. 42. As an example of the input/outputdevice, a touch panel or the like can be given.

FIG. 43 illustrates a structure in which the display device 700illustrated in FIG. 41 includes a touch panel 791. FIG. 44 illustrates astructure in which the display device 700 illustrated in FIG. 42includes the touch panel 791.

FIG. 43 is a cross-sectional view of the structure in which the touchpanel 791 is provided in the display device 700 illustrated in FIG. 41,and FIG. 44 is a cross-sectional view of the structure in which thetouch panel 791 is provided in the display device 700 illustrated inFIG. 42.

First, the touch panel 791 illustrated in FIG. 43 and FIG. 44 isdescribed below.

The touch panel 791 illustrated in FIG. 43 and FIG. 44 is what is calledan in-cell touch panel provided between the second substrate 705 and thecoloring film 736. The touch panel 791 is formed on the second substrate705 side before the coloring film 736 is formed.

Note that the touch panel 791 includes the light-blocking film 738, aninsulating film 792, an electrode 793, an electrode 794, an insulatingfilm 795, an electrode 796, and an insulating film 797. A change in thecapacitance between the electrodes 793 and 794 can be detected when anobject such as a finger or a stylus approaches, for example.

A portion in which the electrode 793 intersects with the electrode 794is illustrated in the upper portion of the transistor 750 illustrated inFIG. 43 and FIG. 44. The electrode 796 is electrically connected to thetwo electrodes 793 between which the electrode 794 is sandwiched throughopenings provided in the insulating film 795. Note that a structure inwhich a region where the electrode 796 is provided is provided in thepixel portion 702 is illustrated in FIG. 43 and FIG. 44 as an example;however, one embodiment of the present invention is not limited thereto.For example, the region where the electrode 796 is provided may beprovided in the source driver circuit portion 704.

The electrode 793 and the electrode 794 are provided in a regionoverlapping with the light-blocking film 738. As illustrated in FIG. 43,it is preferable that the electrode 793 not overlap with thelight-emitting element 782. As illustrated in FIG. 44, it is preferablethat the electrode 793 not overlap with the liquid crystal element 775.In other words, the electrode 793 has an opening in a region overlappingwith the light-emitting element 782 and the liquid crystal element 775.That is, the electrode 793 has a mesh shape. With such a structure, theelectrode 793 does not block light emitted from the light-emittingelement 782, or alternatively the electrode 793 does not block lighttransmitted through the liquid crystal element 775. Thus, sinceluminance is hardly reduced even when the touch panel 791 is provided, adisplay device with high visibility and low power consumption can beobtained. Note that the electrode 794 can have a structure similar tothat of the electrode 793.

Since the electrode 793 and the electrode 794 do not overlap with thelight-emitting element 782, a metal material having low transmittancewith respect to visible light can be used for the electrode 793 and theelectrode 794. Furthermore, since the electrode 793 and the electrode794 do not overlap with the liquid crystal element 775, a metal materialhaving low transmittance with respect to visible light can be used forthe electrode 793 and the electrode 794.

Thus, as compared with the case of using an oxide material whosetransmittance of visible light is high, resistance of the electrodes 793and 794 can be reduced, whereby sensitivity of the sensor of the touchpanel can be increased.

For example, a conductive nanowire may be used for the electrodes 793,794, and 796. The nanowire may have a mean diameter of greater than orequal to 1 nm and less than or equal to 100 nm, preferably greater thanor equal to 5 nm and less than or equal to 50 nm, further preferablygreater than or equal to 5 nm and less than or equal to 25 nm. As thenanowire, a carbon nanotube or a metal nanowire such as an Ag nanowire,a Cu nanowire, or an A; nanowire may be used. For example, in the casewhere an Ag nanowire is used for any one of or all of electrodes 793,794, and 796, the transmittance of visible light can be greater than orequal to 89% and the sheet resistance can be greater than or equal to 40Ω/sq. and less than or equal to 100 Ω/sq.

Although the structure of the in-cell touch panel is illustrated in FIG.43 and FIG. 44, one embodiment of the present invention is not limitedthereto. For example, a touch panel formed over the display device 700,what is called an on-cell touch panel, or a touch panel attached to thedisplay device 700, what is called an out-cell touch panel may be used.

In this manner, the display device of one embodiment of the presentinvention can be combined with various types of touch panels.

At least part of this embodiment can be implemented in combination withany of the other embodiments described in this specification asappropriate.

Embodiment 4

In this embodiment, a display device including a semiconductor device ofone embodiment of the present invention is described with reference toFIGS. 47A to 47C.

<4. Circuit Configuration of Display Device>

A display device illustrated in FIG. 47A includes a region includingpixels of display elements (hereinafter referred to as a pixel portion502), a circuit portion that is provided outside the pixel portion 502and includes a circuit for driving the pixels (hereinafter, the circuitportion is referred to as a driver circuit portion 504), circuits havinga function of protecting elements (hereinafter, the circuits arereferred to as protection circuits 506), and a terminal portion 507.Note that the protection circuits 506 are not necessarily provided.

Part or the whole of the driver circuit portion 504 is preferably formedover a substrate over which the pixel portion 502 is formed. Thus, thenumber of components and the number of terminals can be reduced. Whenpart or the whole of the driver circuit portion 504 is not formed overthe substrate over which the pixel portion 502 is formed, the part orthe whole of the driver circuit portion 504 can be mounted by COG ortape automated bonding (TAB).

The pixel portion 502 includes a plurality of circuits for drivingdisplay elements arranged in X (X is a natural number of 2 or more) rowsand Y (Y is a natural number of 2 or more) columns (hereinafter, thecircuits are referred to as pixel circuits 501). The driver circuitportion 504 includes driver circuits such as a circuit for supplying asignal (scan signal) to select a pixel (hereinafter, the circuit isreferred to as a gate driver 504 a) and a circuit for supplying a signal(data signal) to drive a display element in a pixel (hereinafter, thecircuit is referred to as a source driver 504 b).

The gate driver 504 a includes a shift register or the like. The gatedriver 504 a receives a signal for driving the shift register throughthe terminal portion 507 and outputs a signal. For example, the gatedriver 504 a receives a start pulse signal, a clock signal, or the likeand outputs a pulse signal. The gate driver 504 a has a function ofcontrolling the potentials of wirings supplied with scan signals(hereinafter referred to as scan lines GL_1 to GL_X). Note that aplurality of gate drivers 504 a may be provided to control the scanlines GL_1 to GL_X separately. Alternatively, the gate driver 504 a hasa function of supplying an initialization signal. Without being limitedthereto, another signal can be supplied from the gate driver 504 a.

The source driver 504 b includes a shift register or the like. Thesource driver 504 b receives a signal (image signal) from which a datasignal is generated, as well as a signal for driving the shift register,through the terminal portion 507. The source driver 504 b has a functionof generating a data signal to be written to the pixel circuit 501 fromthe image signal. In addition, the source driver 504 b has a function ofcontrolling output of a data signal in response to a pulse signalproduced by input of a start pulse signal, a clock signal, or the like.Furthermore, the source driver 504 b has a function of controlling thepotentials of wirings supplied with data signals (hereinafter referredto as data lines DL_1 to DL_Y). Alternatively, the source driver 504 bhas a function of supplying an initialization signal. Without beinglimited thereto, another signal can be supplied from the source driver504 b.

The source driver 504 b includes a plurality of analog switches, forexample. The source driver 504 b can output, as data signals,time-divided image signals obtained by sequentially turning on theplurality of analog switches. The source driver 504 b may include ashift register or the like.

A pulse signal and a data signal are input to each of the plurality ofpixel circuits 501 through one of the plurality of scan lines GLsupplied with scan signals and one of the plurality of data lines DLsupplied with data signals, respectively. Writing and holding of thedata signal in each of the plurality of pixel circuits 501 arecontrolled by the gate driver 504 a. For example, to the pixel circuit501 in the m-th row and the n-th column (m is a natural number of X orless, and n is a natural number of Y or less), a pulse signal is inputfrom the gate driver 504 a through the scan line GL_m, and a data signalis input from the source driver 504 b through the data line DL_n inaccordance with the potential of the scan line GL_m.

The protection circuit 506 in FIG. 47A is connected to, for example, thescan line GL between the gate driver 504 a and the pixel circuit 501.Alternatively, the protection circuit 506 is connected to the data lineDL between the source driver 504 b and the pixel circuit 501.Alternatively, the protection circuit 506 can be connected to a wiringbetween the gate driver 504 a and the terminal portion 507.Alternatively, the protection circuit 506 can be connected to a wiringbetween the source driver 504 b and the terminal portion 507. Note thatthe terminal portion 507 refers to a portion having terminals forinputting power, control signals, and image signals from externalcircuits to the display device.

The protection circuit 506 electrically connects a wiring connected tothe protection circuit to another wiring when a potential out of acertain range is supplied to the wiring connected to the protectioncircuit.

As illustrated in FIG. 47A, the protection circuits 506 provided for thepixel portion 502 and the driver circuit portion 504 can improve theresistance of the display device to overcurrent generated byelectrostatic discharge (ESD) or the like. Note that the configurationof the protection circuits 506 is not limited thereto; for example, theprotection circuit 506 can be connected to the gate driver 504 a or thesource driver 504 b. Alternatively, the protection circuit 506 can beconnected to the terminal portion 507.

One embodiment of the present invention is not limited to the example inFIG. 47A, in which the driver circuit portion 504 includes the gatedriver 504 a and the source driver 504 b. For example, only the gatedriver 504 a may be formed, and a separately prepared substrate overwhich a source driver circuit is formed (e.g., a driver circuit boardformed using a single crystal semiconductor film or a polycrystallinesemiconductor film) may be mounted.

Each of the plurality of pixel circuits 501 in FIG. 47A can have theconfiguration illustrated in FIG. 47B, for example.

The pixel circuit 501 in FIG. 47B includes a liquid crystal element 570,a transistor 550, and a capacitor 560. As the transistor 550, thetransistor described in the above embodiment can be used.

The potential of one of a pair of electrodes of the liquid crystalelement 570 is set as appropriate in accordance with the specificationsof the pixel circuit 501. The alignment state of the liquid crystalelement 570 depends on data written thereto. A common potential may besupplied to the one of the pair of electrodes of the liquid crystalelement 570 included in each of the plurality of pixel circuits 501. Thepotential supplied to the one of the pair of electrodes of the liquidcrystal element 570 in the pixel circuit 501 may differ between rows.

Examples of a method for driving the display device including the liquidcrystal element 570 include a TN mode, an STN mode, a VA mode, anaxially symmetric aligned micro-cell (ASM) mode, an opticallycompensated birefringence (OCB) mode, a ferroelectric liquid crystal(FLC) mode, an anti-ferroelectric liquid crystal (AFLC) mode, an MVAmode, a patterned vertical alignment (PVA) mode, an IPS mode, an FFSmode, and a transverse bend alignment (TBA) mode. Other examples of themethod for driving the display device include an electrically controlledbirefringence (ECB) mode, a polymer-dispersed liquid crystal (PDLC)mode, a polymer network liquid crystal (PNLC) mode, and a guest-hostmode. Without being limited thereto, various liquid crystal elements anddriving methods can be used.

In the pixel circuit 501 in the m-th row and the n-th column, one of asource electrode and a drain electrode of the transistor 550 iselectrically connected to the data line DL_n, and the other of thesource electrode and the drain electrode of the transistor 550 iselectrically connected to the other of the pair of electrodes of theliquid crystal element 570. A gate electrode of the transistor 550 iselectrically connected to the scan line GL_m. The transistor 550 isconfigured to be turned on or off to control whether a data signal iswritten.

One of a pair of electrodes of the capacitor 560 is electricallyconnected to a wiring through which a potential is supplied (hereinafterreferred to as a potential supply line VL), and the other of the pair ofelectrodes of the capacitor 560 is electrically connected to the otherof the pair of electrodes of the liquid crystal element 570. Thepotential of the potential supply line VL is set as appropriate inaccordance with the specifications of the pixel circuit 501. Thecapacitor 560 functions as a storage capacitor for storing written data.

For example, in the display device including the pixel circuits 501 inFIG. 47B, the gate driver 504 a in FIG. 47A sequentially selects thepixel circuits 501 row by row to turn on the transistors 550, and datasignals are written.

When the transistor 550 is turned off, the pixel circuit 501 to whichthe data has been written is brought into a holding state. Thisoperation is sequentially performed row by row; thus, an image can bedisplayed.

Alternatively, each of the plurality of pixel circuits 501 in FIG. 47Acan have the configuration illustrated in FIG. 47C, for example.

The pixel circuit 501 in FIG. 47C includes transistors 552 and 554, acapacitor 562, and a light-emitting element 572. The transistordescribed in the above embodiment can be used as the transistor 552and/or the transistor 554.

One of a source electrode and a drain electrode of the transistor 552 iselectrically connected to a wiring through which a data signal issupplied (hereinafter referred to as a data line DL_n). A gate electrodeof the transistor 552 is electrically connected to a wiring throughwhich a gate signal is supplied (hereinafter referred to as a scan lineGL_m).

The transistor 552 is configured to be turned on or off to controlwhether a data signal is written.

One of a pair of electrodes of the capacitor 562 is electricallyconnected to a wiring through which a potential is supplied (hereinafterreferred to as a potential supply line VL_a), and the other of the pairof electrodes of the capacitor 562 is electrically connected to theother of the source electrode and the drain electrode of the transistor552.

The capacitor 562 functions as a storage capacitor for storing writtendata.

One of a source electrode and a drain electrode of the transistor 554 iselectrically connected to the potential supply line VL_a. A gateelectrode of the transistor 554 is electrically connected to the otherof the source electrode and the drain electrode of the transistor 552.

One of an anode and a cathode of the light-emitting element 572 iselectrically connected to a potential supply line VL_b, and the other ofthe anode and the cathode of the light-emitting element 572 iselectrically connected to the other of the source electrode and thedrain electrode of the transistor 554.

As the light-emitting element 572, an organic electroluminescent element(also referred to as an organic EL element) can be used, for example.Note that the light-emitting element 572 is not limited thereto and maybe an inorganic EL element including an inorganic material.

A high power supply potential VDD is supplied to one of the potentialsupply line VL_a and the potential supply line VL_b, and a low powersupply potential V_(SS) is supplied to the other of the potential supplyline VL_a and the potential supply line VL_b.

In the display device including the pixel circuits 501 in FIG. 47C, thegate driver 504 a in FIG. 47A sequentially selects the pixel circuits501 row by row to turn on the transistors 552, and data signals arewritten.

When the transistor 552 is turned off, the pixel circuit 501 to whichthe data has been written is brought into a holding state. Furthermore,the amount of current flowing between the source electrode and the drainelectrode of the transistor 554 is controlled in accordance with thepotential of the written data signal. The light-emitting element 572emits light with a luminance corresponding to the amount of flowingcurrent. This operation is sequentially performed row by row; thus, animage can be displayed.

At least part of this embodiment can be implemented in combination withany of the other embodiments described in this specification asappropriate.

Embodiment 5

In this embodiment, a display module and electronic devices, each ofwhich includes a semiconductor device of one embodiment of the presentinvention, are described with reference to FIG. 48, FIGS. 49A to 49E,FIGS. 50A to 50G, and FIGS. 51A and 51B.

<5-1. Display Module>

In a display module 7000 illustrated in FIG. 48, a touch panel 7004connected to an FPC 7003, a display panel 7006 connected to an FPC 7005,a backlight 7007, a frame 7009, a printed-circuit board 7010, and abattery 7011 are provided between an upper cover 7001 and a lower cover7002.

The semiconductor device of one embodiment of the present invention canbe used for the display panel 7006, for example.

The shapes and sizes of the upper cover 7001 and the lower cover 7002can be changed as appropriate in accordance with the sizes of the touchpanel 7004 and the display panel 7006.

The touch panel 7004 can be a resistive touch panel or a capacitivetouch panel and overlap with the display panel 7006. Alternatively, acounter substrate (sealing substrate) of the display panel 7006 can havea touch panel function. Alternatively, a photosensor may be provided ineach pixel of the display panel 7006 to form an optical touch panel.

The backlight 7007 includes a light source 7008. One embodiment of thepresent invention is not limited to the structure in FIG. 48, in whichthe light source 7008 is provided over the backlight 7007. For example,a structure in which the light source 7008 is provided at an end portionof the backlight 7007 and a light diffusion plate is further providedmay be employed. Note that the backlight 7007 need not be provided inthe case where a self-luminous light-emitting element such as an organicEL element is used or in the case where a reflective panel or the likeis employed.

The frame 7009 protects the display panel 7006 and functions as anelectromagnetic shield for blocking electromagnetic waves generated bythe operation of the printed-circuit board 7010. The frame 7009 may alsofunction as a radiator plate.

The printed-circuit board 7010 includes a power supply circuit and asignal processing circuit for outputting a video signal and a clocksignal. As a power source for supplying power to the power supplycircuit, an external commercial power source or the separate battery7011 may be used. The battery 7011 can be omitted in the case where acommercial power source is used.

The display module 7000 may be additionally provided with a member suchas a polarizing plate, a retardation plate, or a prism sheet.

<5-2. Electronic Device 1>

Next, FIGS. 49A to 49E illustrate examples of electronic devices.

FIG. 49A is an external view of a camera 8000 to which a finder 8100 isattached.

The camera 8000 includes a housing 8001, a display portion 8002, anoperation button 8003, a shutter button 8004, and the like. Furthermore,an attachable lens 8006 is attached to the camera 8000.

Although the lens 8006 of the camera 8000 here is detachable from thehousing 8001 for replacement, the lens 8006 may be included in thehousing 8001.

Images can be taken with the camera 8000 at the press of the shutterbutton 8004. In addition, images can be taken at the touch of thedisplay portion 8002 that serves as a touch panel.

The housing 8001 of the camera 8000 includes a mount including anelectrode, so that the finder 8100, a stroboscope, or the like can beconnected to the housing 8001.

The finder 8100 includes a housing 8101, a display portion 8102, abutton 8103, and the like.

The housing 8101 includes a mount for engagement with the mount of thecamera 8000 so that the finder 8100 can be connected to the camera 8000.The mount includes an electrode, and an image or the like received fromthe camera 8000 through the electrode can be displayed on the displayportion 8102.

The button 8103 serves as a power button. The display portion 8102 canbe turned on and off with the button 8103.

A display device of one embodiment of the present invention can be usedin the display portion 8002 of the camera 8000 and the display portion8102 of the finder 8100.

Although the camera 8000 and the finder 8100 are separate and detachableelectronic devices in FIG. 49A, the housing 8001 of the camera 8000 mayinclude a finder having a display device.

FIG. 49B is an external view of a head-mounted display 8200.

The head-mounted display 8200 includes a mounting portion 8201, a lens8202, a main body 8203, a display portion 8204, a cable 8205, and thelike. The mounting portion 8201 includes a battery 8206.

Power is supplied from the battery 8206 to the main body 8203 throughthe cable 8205. The main body 8203 includes a wireless receiver or thelike to receive video data, such as image data, and display it on thedisplay portion 8204. The movement of the eyeball and the eyelid of auser is captured by a camera in the main body 8203 and then coordinatesof the points the user looks at are calculated using the captured datato utilize the eye of the user as an input means.

The mounting portion 8201 may include a plurality of electrodes so as tobe in contact with the user. The main body 8203 may be configured tosense current flowing through the electrodes with the movement of theuser's eyeball to recognize the direction of his or her eyes. The mainbody 8203 may be configured to sense current flowing through theelectrodes to monitor the user's pulse. The mounting portion 8201 mayinclude sensors, such as a temperature sensor, a pressure sensor, or anacceleration sensor so that the user's biological information can bedisplayed on the display portion 8204. The main body 8203 may beconfigured to sense the movement of the user's head or the like to movean image displayed on the display portion 8204 in synchronization withthe movement of the user's head or the like.

The display device of one embodiment of the present invention can beused in the display portion 8204.

FIGS. 49C to 49E are external views of a head-mounted display 8300. Thehead-mounted display 8300 includes a housing 8301, a display portion8302, an object for fixing, such as a band, 8304, and a pair of lenses8305.

A user can see display on the display portion 8302 through the lenses8305. It is favorable that the display portion 8302 be curved. When thedisplay portion 8302 is curved, a user can feel high realistic sensationof images. Although the structure described in this embodiment as anexample has one display portion 8302, the number of the display portions8302 provided is not limited to one. For example, two display portions8302 may be provided, in which case one display portion is provided forone corresponding user's eye, so that three-dimensional display usingparallax or the like is possible.

The display device of one embodiment of the present invention can beused in the display portion 8302. The display device including thesemiconductor device of one embodiment of the present invention has anextremely high resolution; thus, even when an image is magnified usingthe lenses 8305 as illustrated in FIG. 49E, the user does not perceivepixels, and thus a more realistic image can be displayed.

<5-3. Electronic Device 2>

Next, FIGS. 50A to 50G illustrate examples of electronic devices thatare different from those illustrated in FIGS. 49A to 49E.

Electronic devices illustrated in FIGS. 50A to 50G include a housing9000, a display portion 9001, a speaker 9003, an operation key 9005(including a power switch or an operation switch), a connection terminal9006, a sensor 9007 (a sensor having a function of measuring force,displacement, position, speed, acceleration, angular velocity,rotational frequency, distance, light, liquid, magnetism, temperature,chemical substance, sound, time, hardness, electric field, current,voltage, electric power, radiation, flow rate, humidity, gradient,oscillation, odor, or infrared ray), a microphone 9008, and the like.

The electronic devices in FIGS. 50A to 50G have a variety of functionssuch as a function of displaying a variety of information (e.g., a stillimage, a moving image, and a text image) on the display portion, a touchpanel function, a function of displaying a calendar, date, time, and thelike, a function of controlling processing with a variety of software(programs), a wireless communication function, a function of beingconnected to a variety of computer networks with a wirelesscommunication function, a function of transmitting and receiving avariety of data with a wireless communication function, and a functionof reading out a program or data stored in a memory medium anddisplaying it on the display portion. Note that functions of theelectronic devices in FIGS. 50A to 50G are not limited thereto, and theelectronic devices can have a variety of functions. Although notillustrated in FIGS. 50A to 50G, the electronic devices may each have aplurality of display portions. Furthermore, the electronic devices mayeach be provided with a camera and the like to have a function of takinga still image, a function of taking a moving image, a function ofstoring the taken image in a memory medium (an external memory medium ora memory medium incorporated in the camera), a function of displayingthe taken image on the display portion, or the like.

The electronic devices in FIGS. 50A to 50G are described in detailbelow.

FIG. 50A is a perspective view illustrating a television device 9100.The television device 9100 can include the display portion 9001 having alarge screen size of, for example, 50 inches or more, or 100 inches ormore.

FIG. 50B is a perspective view of a portable information terminal 9101.The portable information terminal 9101 functions as, for example, one ormore of a telephone set, a notebook, and an information browsing system.Specifically, the portable information terminal 9101 can be used as asmartphone. Note that the portable information terminal 9101 may includea speaker, a connection terminal, a sensor, or the like. The portableinformation terminal 9101 can display text and image information on itsplurality of surfaces. For example, three operation buttons 9050 (alsoreferred to as operation icons or simply as icons) can be displayed onone surface of the display portion 9001. Furthermore, information 9051indicated by dashed rectangles can be displayed on another surface ofthe display portion 9001. Examples of the information 9051 includedisplay indicating reception of an e-mail, a social networking service(SNS) message, or a telephone call, the title and sender of an e-mail oran SNS message, date, time, remaining battery, and reception strength ofan antenna. Alternatively, the operation buttons 9050 or the like may bedisplayed in place of the information 9051.

FIG. 50C is a perspective view of a portable information terminal 9102.The portable information terminal 9102 has a function of displayinginformation on three or more surfaces of the display portion 9001. Here,information 9052, information 9053, and information 9054 are displayedon different surfaces. For example, a user of the portable informationterminal 9102 can see the display (here, the information 9053) on theportable information terminal 9102 put in a breast pocket of his/herclothes. Specifically, a caller's phone number, name, or the like of anincoming call is displayed in a position that can be seen from above theportable information terminal 9102. The user can see the display withouttaking out the portable information terminal 9102 from the pocket anddecide whether to answer the call.

FIG. 50D is a perspective view of a watch-type portable informationterminal 9200. The portable information terminal 9200 is capable ofexecuting a variety of applications such as mobile phone calls,e-mailing, reading and editing texts, music reproduction, Internetcommunication, and a computer game. The display surface of the displayportion 9001 is curved, and display can be performed on the curveddisplay surface. The portable information terminal 9200 can employ nearfield communication conformable to a communication standard. Forexample, hands-free calling can be achieved by mutual communicationbetween the portable information terminal 9200 and a headset capable ofwireless communication. Moreover, the portable information terminal 9200includes the connection terminal 9006 and can perform direct datacommunication with another information terminal via a connector.Charging through the connection terminal 9006 is also possible. Notethat the charging operation may be performed by wireless power feedingwithout using the connection terminal 9006.

FIGS. 50E, 50F, and 50G are perspective views of a foldable portableinformation terminal 9201 that is opened, that is shifted from theopened state to the folded state or from the folded state to the openedstate, and that is folded, respectively. The portable informationterminal 9201 is highly portable when folded. When the portableinformation terminal 9201 is opened, a seamless large display region ishighly browsable. The display portion 9001 of the portable informationterminal 9201 is supported by three housings 9000 joined by hinges 9055.By being folded at the hinges 9055 between the two adjacent housings9000, the portable information terminal 9201 can be reversibly changedin shape from the opened state to the folded state. For example, theportable information terminal 9201 can be bent with a radius ofcurvature greater than or equal to 1 mm and less than or equal to 150mm.

Next, an example of an electronic device that is different from theelectronic devices illustrated in FIGS. 49A to 49E and FIGS. 50A to 50Gis illustrated in FIGS. 51A and 51B. FIGS. 51A and 51B are perspectiveviews of a display device including a plurality of display panels. Theplurality of display panels are wound in the perspective view in FIG.51A and are unwound in the perspective view in FIG. 51B.

A display device 9500 illustrated in FIGS. 51A and 51B includes aplurality of display panels 9501, a hinge 9511, and a bearing 9512. Theplurality of display panels 9501 each include a display region 9502 anda light-transmitting region 9503.

Each of the plurality of display panels 9501 is flexible. Two adjacentdisplay panels 9501 are provided so as to partly overlap with eachother. For example, the light-transmitting regions 9503 of the twoadjacent display panels 9501 can overlap with each other. A displaydevice having a large screen can be obtained with the plurality ofdisplay panels 9501. The display device is highly versatile because thedisplay panels 9501 can be wound depending on its use.

Although the display regions 9502 of the adjacent display panels 9501are separated from each other in FIGS. 51A and 51B, without limitationto this structure, the display regions 9502 of the adjacent displaypanels 9501 may overlap with each other without any space so that acontinuous display region 9502 is obtained, for example.

The electronic devices described in this embodiment are characterized byhaving a display portion for displaying some sort of information. Notethat the semiconductor device of one embodiment of the present inventioncan also be used for an electronic device that does not have a displayportion.

At least part of this embodiment can be implemented in combination withany of the other embodiments described in this specification asappropriate.

Example 1

In this example, results of observation and elemental analysis ofIn—Ga—Zn oxide films (hereinafter referred to as IGZO films) formed bythe method described in the above embodiment will be described.

An IGZO film of a sample of this example was formed over a glasssubstrate with the intended thickness set to 100 nm by a sputteringmethod using an In—Ga—Zn oxide target (with an atomic ratio ofIn:Ga:Zn=5:1:7). The IGZO film was formed in an atmosphere including anargon gas at 200 sccm, where the pressure was controlled to 0.6 Pa, thesubstrate temperature was room temperature, and an alternating-currentpower of 2.5 kW was applied.

The formed IGZO film of the sample was observed by HAADF-STEM and wassubjected to measurement using EDX. With the use of an atomic resolutionanalytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.,the HAADF-STEM image was taken and the EDX measurement was performedunder conditions where the acceleration voltage was 200 kV, andirradiation with an electron beam with a diameter of approximately 0.1nmϕ was performed.

In the EDX measurement, an energy dispersive X-ray spectrometerJED-2300T was used as an elemental analysis apparatus. A Si driftdetector was used to detect X-rays emitted from the sample.

In the EDX measurement, an EDX spectrum of a point is obtained in such amanner that electron beam irradiation is performed on the point in ananalysis target region of a sample, and the energy of characteristicX-rays of the sample generated by the irradiation and its frequency aremeasured. In this example, peaks of an EDX spectrum of the point wereattributed to electron transition to the L shell in an In atom, electrontransition to the K shell in a Ga atom, and electron transition to the Kshell in a Zn atom and the K shell in an O atom, and the proportions ofthe atoms in the point were calculated. An EDX mapping image indicatingdistributions of the proportions of the atoms can be obtained throughthis process in an analysis target region of the sample.

FIGS. 52A to 52E and FIGS. 53A to 53E show the HAADF-STEM images and EDXmapping images of the IGZO film of the sample. FIGS. 52A to 52E show theHAADF-STEM images and EDX mapping images of a plane of the IGZO film,and FIGS. 53A to 53E show those of a cross section of the IGZO film.FIG. 52A and FIG. 53A are the HAADF-STEM images of the sample. FIG. 52Band FIG. 53B are EDX mapping images of O atoms, FIG. 52C and FIG. 53Care EDX mapping images of Zn atoms, FIG. 52D and FIG. 53D are EDXmapping images of Ga atoms, and FIG. 52E and FIG. 53E are EDX mappingimages of In atoms. Note that the HAADF-STEM images and EDX mappingimages in FIGS. 52A to 52E and FIGS. 53A to 53E were taken at amagnification of 7,200,000 times.

Bars above the EDX mapping images shown in FIGS. 52B to 52E and FIGS.53B to 53E indicate the proportions [atomic %] of atoms in some pointsof the IGZO film.

The EDX mapping images in FIGS. 52B to 52E and FIGS. 53B to 53E showrelative distribution of brightness indicating that the atoms havedistributions in the IGZO film. Here, attention is focused on OutlinedSquare 1A and Outlined Square 1B in FIGS. 52B to 52E and Outlined Square2A and Outlined Square 2B in FIGS. 53B to 53E.

In FIG. 52E and FIG. 53E, a relatively bright region occupies a largearea in each of Outlined Squares 1A and 2A, while a relatively darkregion occupies a large area in each of Outlined Squares 1B and 2B. Thatis, the number of In atoms is relatively large in the regions indicatedby Outlined Squares 1A and 2A and the number of In atoms is relativelysmall in the regions indicated by Outlined Squares 1B and 2B. In FIG.52E and FIG. 53E, the relatively bright regions correspond to Regions A1described in the above embodiment, and the relatively dark regionscorrespond to Regions B1 described in the above embodiment.

In contrast to FIG. 52E and FIG. 53E, in FIG. 52D and FIG. 53D, arelatively dark region occupies a large area in each of Outlined Squares1A and 2A, while a relatively bright region occupies a large area ineach of Outlined Squares 1B and 2B. That is, the number of Ga atoms isrelatively small in the regions indicated by Outlined Squares 1A and 2Aand the number of Ga atoms is relatively large in the regions indicatedby Outlined Squares 1B and 2B. In this manner, the number of Ga atomstends to be relatively small in the region including a relatively largenumber of In atoms, and the number of Ga atoms tends to be relativelylarge in the region including a relatively small number of In atoms.Accordingly, in FIG. 52D and FIG. 53D, the relatively bright regionsroughly correspond to Regions B1 described in the above embodiment, andthe relatively dark regions roughly correspond to Regions A1 describedin the above embodiment.

In FIG. 52C and FIG. 53C, a relatively bright region occupies a largearea in each of Outlined Square 1B and Outlined Square 2B, whileOutlined Square 1A and Outlined Square 2A each include a bright regionwhose area is not as large as that of the relatively bright region inOutlined Square 1B and Outlined Square 2B. In other words, the number ofZn atoms is relatively large in the regions indicated by Outlined Square1B and Outlined Square 2B, and the number of Zn atoms in the regionsindicated by Outlined Square 1A and Outlined Square 2A is not as largeas that in the regions indicated by Outlined Square 1B and OutlinedSquare 2B.

As for FIG. 52B and FIG. 53B, similarly, the number of oxygen atoms isrelatively large in the regions indicated by Outlined Square 1A,Outlined Square 1B, Outlined Square 2A, and Outlined Square 2B.

As described above, Region A1 of the IGZO film includes a large numberof In atoms and a large number of O atoms and also includes a smallernumber of Zn atoms than Region B1. It is thus suggested that Region A1has a high content of, for example, indium, indium oxide, and an In—Znoxide. Accordingly, Region A1 serves as a region having higherconductivity than Region B1, so that Region A1 contributes to increasesin field-effect mobility and on-state current of a transistor.

Here, when the regions that correspond to Regions A1 (e.g., OutlinedSquare 1A and Outlined Square 2A) in FIG. 52E and FIG. 53E are examined,a plurality of particulate portions can be seen in Region A1.Observation of the particulate portions shows that they have a diameterof greater than or equal to 0.5 nm and less than or equal to 1.5 nm.Regions A1 appear to be formed by the plurality of particulate portionsthat are connected to each other. In this manner, Regions A1 extend in acloud-like manner. The particulate portions included in Regions A1correspond to the clusters in Regions A1 described in the aboveembodiment.

Furthermore, Region B1 of the IGZO film includes a large number of Gaatoms, a large number of Zn atoms, and a large number of O atoms andalso includes a smaller number of In atoms than Region A1. It is thussuggested that Region B1 has a high content of, for example, an In—Ga—Znoxide. Accordingly, Region B1 serves as a region having a highersemiconductor property than Region A1, so that Region B1 contributes tothe switching characteristics of a transistor.

Here, when the regions that correspond to Regions B1 (e.g., OutlinedSquare 1B and Outlined Square 2B) in FIG. 52D and FIG. 53D are examined,a plurality of particulate portions can be seen in Region B1. Regions B1also appear to be formed by the plurality of particulate portions thatare connected to each other. In this manner, Regions B1 also extend in acloud-like manner. The particulate portions included in Regions B1correspond to the clusters in Regions B1 described in the aboveembodiment.

As described above, the IGZO film of the sample fabricated in thisexample is a composite oxide semiconductor where In-rich Regions A1 andIn-poor Regions B1 are formed. Region A1 contributes to the on-statecurrent and field-effect mobility of a transistor, and Region B1contributes to the switching characteristics of a transistor. Therefore,with the use of the composite oxide semiconductor, a transistor withelectrical characteristics in which the on-state current and themobility are high and the S value is small can be manufactured.

At least part of this example can be implemented in combination with anyof the embodiments and the other examples described in thisspecification as appropriate.

Example 2

In this example, composite oxide semiconductors were deposited and theircrystallinities were examined by XRD.

[Fabrication of Sample]

In this example, samples including oxide semiconductor films werefabricated with different oxygen flow rate percentages and substratetemperatures during the deposition.

Each sample was fabricated by forming an oxide semiconductor film over a600 mm×720 mm glass substrate.

Note that the oxide semiconductor film was formed under the followingconditions: a deposition gas(es) with a flow rate of 200 sccm was/wereintroduced into a chamber of the sputtering apparatus; the pressure wasset to 0.6 Pa; and an AC power of 2.5 kW was applied to a metal oxidetarget containing indium, gallium, and zinc (with an atomic ratio ofIn:Ga:Zn=5:1:7).

Here, 18 kinds of samples were fabricated in total using three substratetemperatures and six oxygen flow rate percentages. The substratetemperature during the deposition was room temperature, 130° C., or 170°C. The oxygen flow rate percentage was 0%, 10%, 30%, 50%, 70%, or 100%.The proportions of an oxygen gas and an argon gas were varied such thatthe sum of the oxygen gas flow rate and the argon gas flow rate was 200sccm.

[XRD Analysis Result]

The XRD analysis was conducted by a powder method (also referred to as a0-20 method) which is a kind of an out-of-plane method. Note that in a8-20 method, X-ray diffraction intensity is measured while an incidentangle of an X-ray is changed and the angle of a detector facing an X-raysource is equal to the incident angle. Note that a grazing-incidence XRD(GIXRD) method (also referred to as a thin film method or aSeemann-Bohlin method) may be used. The GIXRD method is a kind of anout-of-plane method for measuring X-ray diffraction intensity in whichX-ray is incident at an angle approximately 0.40° from a film surfacewith use of a variable-angle detector.

FIG. 54 shows the results of the XRD analysis conducted on the samples.In FIG. 54, the horizontal axis represents the diffraction angle 20 andthe vertical axis represents diffraction intensity (any unit). Each ofthe graphs in FIG. 54 shows three diffraction profiles obtained from therespective measurement points. In each graph, the upper and lowerprofiles were obtained from the center of the substrate (A) and theperiphery of the substrate (C), respectively, and the middle profile wasobtained from a point between A and C.

The diffraction angle (around at 2θ=31°) at which the peak of thediffraction intensity was observed corresponds to a diffraction angle onthe (009) plane of the structure model of single crystal InGaZnO₄. Thisindicates that the samples from which the peak of the diffractionintensity was observed include a crystal part where the c-axes arealigned in the thickness direction (hereinafter also referred to ascrystal part having orientation).

As seen in FIG. 54, no clear peak is observed from the film deposited atroom temperature and with an oxygen flow rate percentage of 0%. Thissuggests that the proportion of crystal parts having orientation in thefilm is extremely low.

Meanwhile, clear peaks are observed from the films that were depositedat room temperature using the deposition gas containing oxygen. The peakintensities of the films deposited at room temperature and with anoxygen flow rate percentage of higher than or equal to 70% tend to below.

Furthermore, clear peaks are observed from the films that were depositedwith an oxygen flow rate percentage of 0% at high substratetemperatures. At substrate temperatures of 130° C. and 170° C., clearerpeaks are observed in the case of using the deposition gas containingoxygen. The peak intensities of the films deposited with high oxygenflow rate percentages (higher than or equal to 70%) tend to be low, asin the films deposited at room temperature.

The above-described results show that the crystallinity of an oxidesemiconductor film to be deposited can be controlled with the oxygenflow rate percentage and substrate temperature during the deposition. Itwas also found that the crystallinity can be high by setting thesubstrate temperature high even when the oxygen flow rate percentage is0%. Moreover, it was found that the crystallinity can be high by settingthe oxygen flow rate percentage high even when the substrate temperatureis room temperature.

At least part of this example can be implemented in combination with anyof the embodiments and the other examples described in thisspecification as appropriate.

Example 3

In this example, a transistor which corresponds to the transistor 100Adescribed in Embodiment 2 was formed and the electrical characteristicsof the transistor were evaluated. In this example, Sample S1 describedbelow was fabricated. Sample S1 is a sample in which a transistor with achannel length L of 3 μm and a channel width W of 50 μm is formed.

[Fabrication Method of Sample S1]

First, a 10-nm-thick titanium film and a 100-nm-thick copper film wereformed over a glass substrate with a sputtering apparatus. Next, theconductive film was processed by a photolithography method.

A stack including four insulating films was formed over the substrateand the conductive film. The insulating films were formed in successionin a vacuum with a plasma-enhanced chemical deposition (PECVD)apparatus. As the insulating films, a 50-nm-thick silicon nitride film,a 300-nm-thick silicon nitride film, a 50-nm-thick silicon nitride film,and a 50-nm-thick silicon oxynitride film were used and stacked in thisorder.

Next, an oxide semiconductor film was formed over the insulating filmsand was processed into an island shape, whereby a semiconductor layerwas formed. A 40-nm-thick oxide semiconductor film was formed as theoxide semiconductor film 108. The oxide semiconductor film is theabove-described composite oxide semiconductor or C/IGZO.

The oxide semiconductor film was formed under the following conditions:the substrate temperature was room temperature (25° C.); an argon gaswith a flow rate of 200 sccm was introduced into a chamber of thesputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of2.5 kW was applied to a metal oxide target containing indium, gallium,and zinc (with an atomic ratio of In:Ga:Zn=5:1:7). In this example, theoxygen flow rate percentage in deposition of the oxide semiconductorfilm was 0%.

Next, an insulating film was formed over the insulating films and thesemiconductor layer. As the insulating film, a 150-nm-thick siliconoxynitride film was formed with a PECVD apparatus.

Next, heat treatment was performed. The heat treatment was performed at350° C. for one hour in a mixed gas atmosphere of nitrogen and oxygen.

An opening was formed in a desired region of the insulating film. Theopening was formed by a dry etching method.

Then, a conductive film was formed over the insulating film and in theopening and the conductive film was processed into an island shape. Inaddition, the insulating film in contact with the bottom surface of theconductive film was processed in succession after the formation of theconductive film, whereby the insulating film was formed.

As the conductive film, a 10-nm-thick oxide semiconductor film, a50-nm-thick titanium nitride film, and a 100-nm-thick copper film wereformed in this order. The oxide semiconductor film was formed under thefollowing conditions: the substrate temperature was 170° C.; an oxygengas with a flow rate of 200 sccm was introduced into a chamber of thesputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of2.5 kW was applied to a metal oxide target containing indium, gallium,and zinc (with an atomic ratio of In:Ga:Zn=4:2:4.1). The titaniumnitride film and the copper film were each formed using a sputteringapparatus.

Next, plasma treatment was performed from above the semiconductor layer,the insulating film, and the conductive film. The plasma treatment wasperformed with a PECVD apparatus at a substrate temperature of 220° C.in a mixed gas atmosphere containing an argon gas and a nitrogen gas.

Next, an insulating film was formed over the semiconductor layer, theinsulating film, and the conductive film. The insulating film was formedby stacking a 100-nm-thick silicon nitride film and a 300-nm-thicksilicon oxynitride film with a PECVD apparatus.

Then, a mask was formed over the formed insulating film and an openingwas formed in the insulating film with use of the mask.

A conductive film was formed to fill the opening and was processed intoan island shape, whereby the conductive films serving as a sourceelectrode and a drain electrode were formed. For the conductive films, a10-nm-thick titanium film and a 100-nm-thick copper film were formedwith a sputtering apparatus.

After that, an insulating film was formed over the insulating film andthe conductive film. A 1.5 μm-thick acrylic photosensitive resin wasused for the insulating film.

In the above manner, Sample S1 was fabricated.

[I_(d)-V_(g) Characteristics of Transistor]

Next, I_(d)-V_(g) characteristics of the fabricated transistor of SampleS1 were measured. In measuring the I_(d)-V_(g) characteristics of thetransistor, a voltage applied to the conductive film serving as a firstgate electrode (hereinafter the voltage is also referred to as gatevoltage (V_(g))) and a voltage applied to the conductive film serving asa second gate electrode (hereinafter the voltage is also referred to asback gate voltage (V_(bg))) were changed from −10 V to +10 V inincrements of 0.25 V. A voltage applied to the conductive film servingas the source electrode (hereinafter the voltage is also referred to assource voltage (Vs)) was 0 V (comm) and voltages applied to theconductive film serving as the drain electrode (hereinafter the voltagesare also referred to as drain voltage (V_(d))) were 0.1 V and 20 V.

FIG. 55 shows the results of I_(d)-V_(g) characteristics of Sample S1.In FIG. 55, the first vertical axis represents I_(d) [A], the secondvertical axis represents field-effect mobility (μFE) [cm²/Vs], and thehorizontal axis represents V_(g) [V]. Note that the field-effectmobility was measured when V_(d) was 20 V.

Note that the results in FIG. 55 were obtained with the upper limit ofI_(d) in the measurement set to 1 mA. In FIG. 55, when V_(d) is 20 V,I_(d) exceeds this upper limit at a V_(g) of 7.5 V. For this reason,FIG. 55 shows the field-effect mobility in the range where V_(g) islower than or equal to 7.5 V as the field-effect mobility estimated fromsuch I_(d)-V_(g) characteristics.

The transistor, which is a semiconductor device of one embodiment of thepresent invention, has excellent electrical characteristics as shown inFIG. 55. Here, Table 1 lists the transistor characteristics that areshown in FIG. 55.

TABLE 1 S μFE(@V_(g) = μFE(max)/ μFE(max) V_(th) [V/ I_(off) 2 V)μFE(@V_(g) = [cm²V⁻¹s⁻¹] [V] decade] [A/cm²] [cm²V⁻¹s⁻¹] 2 V) 103 −0.10.12 <1 × 10⁻¹² 70 1.47

As described above, the field-effect mobility of the transistor that isa semiconductor device of one embodiment of the present inventionexceeds 100 cm²/Vs. This field-effect mobility is equivalent to that ofa transistor including low-temperature polysilicon and meansextraordinary characteristics for a transistor using an oxidesemiconductor.

As shown in Table 1, Sample S1 includes a first region where the maximumvalue of the field-effect mobility of the transistor at a gate voltageof higher than 0 V and lower than or equal to 10 V is larger than orequal to 60 cm²/Vs and smaller than 150 cm²/Vs, a second region wherethe threshold voltage is higher than or equal to −1 V and lower than orequal to 1 V, a third region where the S value is smaller than 0.3V/decade, and a fourth region where the off-state current is lower than1×10⁻¹² A/cm², and μ_(FE)(max)/μ_(FE)(V_(g)=2V) is larger than or equalto 1 and smaller than 2 where μ_(FE)(max) represents the maximum valueof the field-effect mobility of the transistor and μ_(FE)(V_(g)=2V)represents the value of the field-effect mobility of the transistor at agate voltage of 2 V.

The above-described characteristics of the transistor can be obtainedwith the use of the composite oxide semiconductor or C/IGZO describedabove. A transistor including the composite oxide semiconductor orC/IGZO in its semiconductor layer can have both high carrier mobilityand excellent switching characteristics.

At least part of this example can be implemented in combination with anyof the embodiments and the other examples described in thisspecification as appropriate.

Example 4

In this example, a transistor which corresponds to the transistor 100Adescribed in Embodiment 2 was formed and the electrical characteristicsand the cross-sectional shape of the transistor were evaluated. In thisexample, Sample S2 described below was fabricated. Sample S2 is a samplein which a transistor with a channel length L of 2 μm and a channelwidth W of 3 μm is formed.

[Fabrication Method of Sample S2]

First, a 10-nm-thick titanium film and a 100-nm-thick copper film wereformed over a glass substrate with a sputtering apparatus. Next, theconductive film was processed by a photolithography method.

A stack including four insulating films was formed over the substrateand the conductive film. The insulating films were formed in successionin a vacuum with a plasma-enhanced chemical deposition (PECVD)apparatus. As the insulating films, a 50-nm-thick silicon nitride film,a 100-nm-thick silicon nitride film, a 50-nm-thick silicon nitride film,and a 50-nm-thick silicon oxynitride film were used and stacked in thisorder.

Next, an oxide semiconductor film was formed over the insulating filmsand was processed into an island shape, whereby a semiconductor layerwas formed. A 40-nm-thick oxide semiconductor film was formed as theoxide semiconductor film 108. The oxide semiconductor film is theabove-described composite oxide semiconductor or C/IGZO.

The oxide semiconductor film was formed under the following conditions:the substrate temperature was 70° C.; an argon gas with a flow rate of180 sccm and an oxygen gas with a flow rate of 20 sccm were introducedinto a chamber of the sputtering apparatus; the pressure was set to 0.6Pa; and an AC power of 2.5 kW was applied to a metal oxide targetcontaining indium, gallium, and zinc (with an atomic ratio ofIn:Ga:Zn=4:2:4.1). In this example, the oxygen flow rate percentage indeposition of the oxide semiconductor film was 10%.

Next, an insulating film was formed over the insulating films and thesemiconductor layer. As the insulating film, a 150-nm-thick siliconoxynitride film was formed with a PECVD apparatus.

Next, heat treatment was performed. The heat treatment was performed at350° C. for one hour in a mixed gas atmosphere of nitrogen and oxygen.

An opening was formed in a desired region of the insulating film. Theopening was formed by a dry etching method.

Then, a conductive film was formed over the insulating film and in theopening and the conductive film was processed into an island shape. Inaddition, the insulating film in contact with the bottom surface of theconductive film was processed in succession after the formation of theconductive film, whereby the insulating film was formed.

As the conductive film, a 10-nm-thick first oxide semiconductor film anda 90-nm-thick second oxide semiconductor film were formed in this order.The first oxide semiconductor film was formed under the followingconditions: the substrate temperature was 170° C.; an oxygen gas with aflow rate of 200 sccm was introduced into a chamber of the sputteringapparatus; the pressure was set to 0.6 Pa; and an AC power of 2.5 kW wasapplied to a metal oxide target containing indium, gallium, and zinc(with an atomic ratio of In:Ga:Zn=4:2:4.1). The second oxidesemiconductor film was formed under the following conditions: thesubstrate temperature was 170° C.; an argon gas with a flow rate of 180sccm and an oxygen gas with a flow rate of 20 sccm were introduced intoa chamber of the sputtering apparatus; the pressure was set to 0.6 Pa;and an AC power of 2.5 kW was applied to a metal oxide target containingindium, gallium, and zinc (with an atomic ratio of In:Ga:Zn=4:2:4.1).

Next, plasma treatment was performed from above the semiconductor layer,the insulating film, and the conductive film. The plasma treatment wasperformed with a PECVD apparatus at a substrate temperature of 220° C.in a mixed gas atmosphere containing an argon gas and a nitrogen gas.

Next, an insulating film was formed over the semiconductor layer, theinsulating film, and the conductive film. The insulating film was formedby stacking a 100-nm-thick silicon nitride film and a 300-nm-thicksilicon oxynitride film with a PECVD apparatus.

Then, a mask was formed over the formed insulating film and an openingwas formed in the insulating film with use of the mask.

A conductive film was formed to fill the opening and was processed intoan island shape, whereby the conductive films serving as a sourceelectrode and a drain electrode were formed. For the conductive films, a50-nm-thick titanium film, a 400-nm-thick aluminum film, and a100-nm-thick titanium film were formed in this order with a sputteringapparatus.

After that, an insulating film was formed over the insulating film andthe conductive film. A 1.5-μm-thick acrylic photosensitive resin wasused for the insulating film.

In the above manner, Sample S2 was fabricated.

[I_(d)-V_(g) Characteristics of Transistor]

Next, I_(d)-V_(g) characteristics of the fabricated transistor of SampleS2 were measured. The measurement conditions of I_(d)-V_(g)characteristics of the transistor were the same as those in Example 3.

FIG. 56 shows the results of I_(d)-V_(g) characteristics of Sample S2.

The transistor, which is a semiconductor device of one embodiment of thepresent invention, has excellent electrical characteristics as shown inFIG. 56. Here, Table 2 lists the transistor characteristics that areshown in FIG. 56.

TABLE 2 S μFE(@V_(g) = μFE(max)/ μFE(max) V_(th) [V/ I_(off) 2 V)μFE(@V_(g) = [cm²V⁻¹s⁻¹] [V] decade] [A/cm²] [cm²V⁻¹s⁻¹] 2 V) 65.5 0.230.09 <1 × 10⁻¹² 58 1.13

As shown in Table 2, Sample S2 includes a first region where the maximumvalue of the field-effect mobility of the transistor at a gate voltageof higher than 0 V and lower than or equal to 10 V is larger than orequal to 60 cm²/Vs and smaller than 150 cm²/Vs, a second region wherethe threshold voltage is higher than or equal to −1 V and lower than orequal to 1 V, a third region where the S value is smaller than 0.3V/decade, and a fourth region where the off-state current is lower than1×10⁻¹² A/cm², and μ_(FE)(max)/μ_(FE)(V_(g)=2V) is larger than or equalto 1 and smaller than 2 where μ_(FE)(max) represents the maximum valueof the field-effect mobility of the transistor and μ_(FE)(V_(g)=2V)represents the value of the field-effect mobility of the transistor at agate voltage of 2 V.

The above-described characteristics of the transistor can be obtainedwith the use of the composite oxide semiconductor or C/IGZO describedabove. A transistor including the composite oxide semiconductor orC/IGZO in its semiconductor layer can have both high carrier mobilityand excellent switching characteristics.

[Cross-Sectional Shape of Transistor]

Next, the cross-sectional shape of the fabricated transistor of SampleS2 was evaluated. Cross-sectional STEM observation was conducted toevaluate the cross-sectional shape of the transistor. FIG. 57 shows across-sectional STEM image of the transistor of Sample S2.

As shown in FIG. 57, Sample S2 fabricated in this example was confirmedto have a favorable cross-sectional shape. The channel length L, whichwas designed to be 2 μm, was found to be 1.78 μm in the completedtransistor.

At least part of this example can be implemented in combination with anyof the embodiments and the other examples described in thisspecification as appropriate.

This application is based on Japanese Patent Application serial no.2016-074493 filed with Japan Patent Office on Apr. 1, 2016 and JapanesePatent Application serial no. 2016-075853 filed with Japan Patent Officeon Apr. 5, 2016, the entire contents of which are hereby incorporated byreference.

What is claimed is:
 1. A composite oxide semiconductor comprising: afirst region; and a second region, wherein the first region and thesecond region are mixed, wherein the first region comprises a pluralityof first clusters comprising one or more of In, Zn, and O as a maincomponent, wherein the second region comprises a plurality of secondclusters comprising one or more of In, an element M, Zn, and O as a maincomponent, wherein, in the first region, at least some of the pluralityof first clusters are connected to each other, wherein, in the secondregion, at least some of the plurality of second clusters are connectedto each other, and wherein the M represents Al, Ga, Y, or Sn.
 2. Thecomposite oxide semiconductor according to claim 1, wherein the firstregion exists being surrounded by the second region.
 3. The compositeoxide semiconductor according to claim 1, wherein an atomic ratio of Into an element M and Zn is represented by In:M:Zn=x:y:z, wherein theatomic ratio of the In to the element M and the Zn is In:M:Zn=4:2:3 orin a neighborhood of In:M:Zn=4:2:3, and wherein y is greater than orequal to 1.5 and less than or equal to 2.5 and z is greater than orequal to 2 and less than or equal to 4 when x is
 4. 4. The compositeoxide semiconductor according to claim 1, wherein an atomic ratio of Intown element M and Zn is represented by In:M:Zn=x:y:z, wherein theatomic ratio of the In to the element M and the Zn is In:M:Zn=5:1:6 orin a neighborhood of In:M:Zn=5:1:6, and wherein y is greater than orequal to 0.5 and less than or equal to 1.5 and z is greater than orequal to 5 and less than or equal to 7 when x is
 5. 5. The compositeoxide semiconductor according to claim 1, wherein the first clustershave higher conductivity than the second clusters, and wherein thesecond clusters have a higher semiconductor property than the firstclusters.
 6. The composite oxide semiconductor according to claim 1,wherein a size of one of the first clusters is greater than or equal to0.5 nm and less than or equal to 1.5 nm.
 7. A semiconductor devicecomprising: a semiconductor layer; a gate; and a gate insulating layer,wherein the semiconductor layer comprises the composite oxidesemiconductor according to claim
 1. 8. The semiconductor deviceaccording to claim 7, wherein a maximum value of field-effect mobilityis greater than or equal to 100 cm²Ns and less than or equal to 200cm²Ns in a range in which a gate voltage is higher than 0 V and lowerthan or equal to 10 V and a drain voltage is higher than 0 V and lowerthan or equal to 20 V.